/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DTS_IMX6UL_PINFUNC_H
#define __DTS_IMX6UL_PINFUNC_H
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
#define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02A0 0x0000 5 0
#define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02A4 0x0000 5 0
#define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001C 0x02A8 0x0000 5 0
#define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02AC 0x0000 5 0
#define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02B0 0x0000 5 0
#define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02B4 0x0000 5 0
#define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002C 0x02B8 0x0000 5 0
#define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02BC 0x0000 5 0
#define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02C0 0x0000 5 0
#define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02C4 0x0000 5 0
#define MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x003C 0x02C8 0x0000 5 0
#define MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x0040 0x02CC 0x0000 5 0
#define MX6UL_PAD_JTAG_MOD__SJC_MOD 0x0044 0x02D0 0x0000 0 0
#define MX6UL_PAD_JTAG_MOD__GPT2_CLK 0x0044 0x02D0 0x05A0 1 0
#define MX6UL_PAD_JTAG_MOD__SPDIF_OUT 0x0044 0x02D0 0x0000 2 0
#define MX6UL_PAD_JTAG_MOD__ENET1_REF_CLK_25M 0x0044 0x02D0 0x0000 3 0
#define MX6UL_PAD_JTAG_MOD__CCM_PMIC_RDY 0x0044 0x02D0 0x04C0 4 0
#define MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0044 0x02D0 0x0000 5 0
#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00 0x0044 0x02D0 0x0000 6 0
#define MX6UL_PAD_JTAG_TMS__SJC_TMS 0x0048 0x02D4 0x0000 0 0
#define MX6UL_PAD_JTAG_TMS__GPT2_CAPTURE1 0x0048 0x02D4 0x0598 1 0
#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x0048 0x02D4 0x0000 2 0
#define MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x0048 0x02D4 0x0000 3 0
#define MX6UL_PAD_JTAG_TMS__CCM_WAIT 0x0048 0x02D4 0x0000 4 0
#define MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x0048 0x02D4 0x0000 5 0
#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01 0x0048 0x02D4 0x0000 6 0
#define MX6UL_PAD_JTAG_TMS__EPIT1_OUT 0x0048 0x02D4 0x0000 8 0
#define MX6UL_PAD_JTAG_TDO__SJC_TDO 0x004C 0x02D8 0x0000 0 0
#define MX6UL_PAD_JTAG_TDO__GPT2_CAPTURE2 0x004C 0x02D8 0x059C 1 0
#define MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x004C 0x02D8 0x05FC 2 0
#define MX6UL_PAD_JTAG_TDO__CCM_CLKO2 0x004C 0x02D8 0x0000 3 0
#define MX6UL_PAD_JTAG_TDO__CCM_STOP 0x004C 0x02D8 0x0000 4 0
#define MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x004C 0x02D8 0x0000 5 0
#define MX6UL_PAD_JTAG_TDO__MQS_RIGHT 0x004C 0x02D8 0x0000 6 0
#define MX6UL_PAD_JTAG_TDO__EPIT2_OUT 0x004C 0x02D8 0x0000 8 0
#define MX6UL_PAD_JTAG_TDI__SJC_TDI 0x0050 0x02DC 0x0000 0 0
#define MX6UL_PAD_JTAG_TDI__GPT2_COMPARE1 0x0050 0x02DC 0x0000 1 0
#define MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x0050 0x02DC 0x05F8 2 0
#define MX6UL_PAD_JTAG_TDI__PWM6_OUT 0x0050 0x02DC 0x0000 4 0
#define MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x0050 0x02DC 0x0000 5 0
#define MX6UL_PAD_JTAG_TDI__MQS_LEFT 0x0050 0x02DC 0x0000 6 0
#define MX6UL_PAD_JTAG_TDI__SIM1_POWER_FAIL 0x0050 0x02DC 0x0000 8 0
#define MX6UL_PAD_JTAG_TCK__SJC_TCK 0x0054 0x02E0 0x0000 0 0
#define MX6UL_PAD_JTAG_TCK__GPT2_COMPARE2 0x0054 0x02E0 0x0000 1 0
#define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0054 0x02E0 0x0000 2 0
#define MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0054 0x02E0 0x0000 4 0
#define MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x0054 0x02E0 0x0000 5 0
#define MX6UL_PAD_JTAG_TCK__SIM2_POWER_FAIL 0x0054 0x02E0 0x0000 8 0
#define MX6UL_PAD_JTAG_TRST_B__SJC_TRSTB 0x0058 0x02E4 0x0000 0 0
#define MX6UL_PAD_JTAG_TRST_B__GPT2_COMPARE3 0x0058 0x02E4 0x0000 1 0
#define MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0058 0x02E4 0x0000 2 0
#define MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0058 0x02E4 0x0000 4 0
#define MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x0058 0x02E4 0x0000 5 0
#define MX6UL_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS 0x0058 0x02E4 0x0000 8 0
#define MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x005C 0x02E8 0x05AC 0 1
#define MX6UL_PAD_GPIO1_IO00__GPT1_CAPTURE1 0x005C 0x02E8 0x058C 1 0
#define MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x005C 0x02E8 0x04B8 2 0
#define MX6UL_PAD_GPIO1_IO00__ENET1_REF_CLK1 0x005C 0x02E8 0x0574 3 0
#define MX6UL_PAD_GPIO1_IO00__MQS_RIGHT 0x005C 0x02E8 0x0000 4 0
#define MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x005C 0x02E8 0x0000 5 0
#define MX6UL_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN 0x005C 0x02E8 0x0000 6 0
#define MX6UL_PAD_GPIO1_IO00__SRC_SYSTEM_RESET 0x005C 0x02E8 0x0000 7 0
#define MX6UL_PAD_GPIO1_IO00__WDOG3_WDOG_B 0x005C 0x02E8 0x0000 8 0
#define MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x0060 0x02EC 0x05B0 0 1
#define MX6UL_PAD_GPIO1_IO01__GPT1_COMPARE1 0x0060 0x02EC 0x0000 1 0
#define MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x0060 0x02EC 0x0664 2 0
#define MX6UL_PAD_GPIO1_IO01__ENET2_REF_CLK2 0x0060 0x02EC 0x057C 3 0
#define MX6UL_PAD_GPIO1_IO01__MQS_LEFT 0x0060 0x02EC 0x0000 4 0
#define MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x0060 0x02EC 0x0000 5 0
#define MX6UL_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT 0x0060 0x02EC 0x0000 6 0
#define MX6UL_PAD_GPIO1_IO01__SRC_EARLY_RESET 0x0060 0x02EC 0x0000 7 0
#define MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x0060 0x02EC 0x0000 8 0
#define MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x0064 0x02F0 0x05A4 0 0
#define MX6UL_PAD_GPIO1_IO02__GPT1_COMPARE2 0x0064 0x02F0 0x0000 1 0
#define MX6UL_PAD_GPIO1_IO02__USB_OTG2_PWR 0x0064 0x02F0 0x0000 2 0
#define MX6UL_PAD_GPIO1_IO02__ENET1_REF_CLK_25M 0x0064 0x02F0 0x0000 3 0
#define MX6UL_PAD_GPIO1_IO02__USDHC1_WP 0x0064 0x02F0 0x066C 4 0
#define MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0064 0x02F0 0x0000 5 0
#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 0x0064 0x02F0 0x0000 6 0
#define MX6UL_PAD_GPIO1_IO02__SRC_ANY_PU_RESET 0x0064 0x02F0 0x0000 7 0
#define MX6UL_PAD_GPIO1_IO02__UART1_DCE_TX 0x0064 0x02F0 0x0000 8 0
#define MX6UL_PAD_GPIO1_IO02__UART1_DTE_RX 0x0064 0x02F0 0x0624 8 0
#define MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x0068 0x02F4 0x05A8 0 1
#define MX6UL_PAD_GPIO1_IO03__GPT1_COMPARE3 0x0068 0x02F4 0x0000 1 0
#define MX6UL_PAD_GPIO1_IO03__USB_OTG2_OC 0x0068 0x02F4 0x0660 2 0
#define MX6UL_PAD_GPIO1_IO03__USDHC1_CD_B 0x0068 0x02F4 0x0668 4