LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY sin IS
PORT(clk,clrn:IN STD_LOGIC; --CLK时钟信号，clrn复位信号
q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); --8位数据输出
END sin;
ARCHITECTURE a OF sin IS
BEGIN
PROCESS(clk,clrn)
VARIABLE tmp:INTEGER RANGE 63 DOWNTO 0;
BEGIN
IF clrn='0' THEN q<=0;tmp:=0;
ELSE IF clk'event AND clk='1'THEN
IF tmp=63 THEN tmp:=0; ELSE tmp:=tmp+1;END IF;
CASE tmp IS
WHEN 0=>q<=255 ;WHEN 1=>q<=254 ;WHEN 2=>q<=252;
WHEN 3=>q<=249 ;WHEN 4=>q<=245 ;WHEN 5=>q<=239;
WHEN 6=>q<=233 ;WHEN 7=>q<=225 ;WHEN 8=>q<=217;
WHEN 9=>q<=207 ;WHEN 10=>q<=197 ;WHEN 11=>q<=186;
WHEN 12=>q<=174 ;WHEN 13=>q<=162 ;WHEN 14=>q<=150;
WHEN 15=>q<=137 ;WHEN 16=>q<=124 ;WHEN 17=>q<=112;
WHEN 18=>q<=99 ;WHEN 19=>q<=87 ;WHEN 20=>q<=75;
WHEN 21=>q<=64 ;WHEN 22=>q<=53 ;WHEN 23=>q<=43;
WHEN 24=>q<=34 ;WHEN 25=>q<=26 ;WHEN 26=>q<=19;
WHEN 27=>q<=13 ;WHEN 28=>q<=8 ;WHEN 29=>q<=4;
WHEN 30=>q<=1 ;WHEN 31=>q<=0 ;WHEN 32=>q<=0;
WHEN 33=>q<=1 ;WHEN 34=>q<=4 ;WHEN 35=>q<=8;
WHEN 36=>q<=13 ;WHEN 37=>q<=19 ;WHEN 38=>q<=26;
WHEN 39=>q<=34 ;WHEN 40=>q<=43 ;WHEN 41=>q<=53;
WHEN 42=>q<=64 ;WHEN 43=>q<=75 ;WHEN 44=>q<=87;
WHEN 45=>q<=99 ;WHEN 46=>q<=112 ;WHEN 47=>q<=124;
WHEN 48=>q<=137 ;WHEN 49=>q<=150 ;WHEN 50=>q<=162;
WHEN 51=>q<=174 ;WHEN 52=>q<=186 ;WHEN 53=>q<=197;
WHEN 54=>q<=207 ;WHEN 55=>q<=217 ;WHEN 56=>q<=225;
WHEN 57=>q<=233 ;WHEN 58=>q<=239 ;WHEN 59=>q<=245;
WHEN 60=>q<=249 ;WHEN 61=>q<=252 ;WHEN 62=>q<=254;
WHEN 63=>q<=255 ;WHEN OTHERS=>NULL;
END CASE;
END IF;
END IF;
END PROCESS;
END a;
vhdl_source.rar_delta vhdl_sin Function vhdl_sin vhdl
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2022-09-21
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