----------------------------------------------------------------
--
-- Copyright (c) 1992,1993,1994, Exemplar Logic Inc. All rights reserved.
--
----------------------------------------------------------------
--
-- This design implements a UART.
--
--
-- Version 1.1 : Original Creation
-- Version 1.2 : Modified to std_logic types
-- Version 2.1 : Extended reset to be more effective.
-- Introduced OTHERS clause.
------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY uart IS
PORT (clkx16 : IN std_logic; -- Input clock. 16x bit clock
read : IN std_logic; -- Received data read strobe
write : IN std_logic; -- Transmit data write strobe
rx : IN std_logic; -- Receive data line
reset : IN std_logic; -- clear dependencies
tx : OUT std_logic; -- Transmit data line
rxrdy : OUT std_logic; -- Received data ready to be read
txrdy : OUT std_logic; -- Transmitter ready for next byte
parityerr : OUT std_logic; -- Receiver parity error
framingerr : OUT std_logic; -- Receiver framing error
overrun : OUT std_logic; -- Receiver overrun error
data : INOUT std_logic_vector(0 TO 7)); -- Bidirectional data bus
END uart;
ARCHITECTURE exemplar OF uart IS
-- Transmit data holding register
SIGNAL txhold : std_logic_vector(0 TO 7);
-- Transmit shift register bits
SIGNAL txreg : std_logic_vector(0 TO 7);
SIGNAL txtag2 : std_logic; -- tag bits for detecting
SIGNAL txtag1 : std_logic; -- empty shift reg
SIGNAL txparity : std_logic; -- Parity generation register
-- Transmit clock and control signals
SIGNAL txclk : std_logic; -- Transmit clock: 1/16th of clkx16
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