Ⅰ代码序列发生：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bak1 is
port( clk,reset: in std_logic;
dout:out std_logic);
end bak1;
architecture a of bak1 is
signal count :std_logic_vector(2 downto 0);
signal tmp1:std_logic;
begin
dout<=tmp1;
process(clk,reset)
begin
if reset='0' then
count<=(others=>'0');
elsif rising_edge(clk) then
count<=count+1;
case count is
when "000"=>tmp1<='1' ;
when "001"=>tmp1<='1' ;
when "010"=>tmp1<='1' ;
when "011"=>tmp1<='0' ;
when "100"=>tmp1<='0' ;
when "101"=>tmp1<='1' ;
when "110"=>tmp1<='0' ;
when "111"=>tmp1<='1' ;
when others=>tmp1<='0';
end case;
end if;
end process;
end a;
码生成仿真图：
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