程 序
附 录 A H D B 3 编 码 程 序 （ 一 ）
library ieee;
use ieee.std_logic_1164.all;
entity bmbm is
port(maliuin:in std_logic;
clk:in std_logic;
clr:in std_logic;
maout:out std_logic_vector(1 downto 0));
end bmbm;
architecture fa1 of bmbm is
signal maoutv:std_logic_vector(1 downto 0);
signal geshu0:integer:=0;
signal register0:std_logic_vector(4 downto 0):="00000";
signal geshu1:integer range 1 downto 0;
signal maoutb:std_logic_vector(1 downto 0);
signal register1:std_logic_vector(4 downto 0):="00000";
signal clkb:std_logic;
signal flag1b:integer range 1 downto 0;
signal flagv:integer range 1 downto 0;
signal firstv:integer range 0 to 1;
component chufa --D 触发器
port(d:in std_logic;
clk:in std_logic;
q:out std_logic);
end component;
begin
add_v:process(clk,clr) ----判断插 V 模块
begin
if(rising_edge(clk))then
if(clr='1')then
maoutv<="00";
geshu0<=0;
else
case maliuin is ----判断输入的是 0 还是 1
when '1'=>maoutv<="01";
geshu0<=0;
when '0'=>
if(geshu0=3)then ----如果是第四个 0，则输出 V
maoutv<="11";
