library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity V2 is --实体hdb3_decode 定义
port(
codein: in std_logic; --高位 --data1为输入高位
clk: in std_logic; --时钟输入信号
clr: in std_logic; --低位 --data0为输入低位
code_out: out std_logic); -- 输出信号
end V2; --结束定义
architecture rtl of V2 is
signal flag:std_logic;
signal count0:integer:=0;
signal codeoutv:std_logic_vector(1 downto 0);
signal s0:std_logic_vector(4 downto 0):="00000";--定义内部信号s0
signal s1:std_logic_vector(4 downto 0):="00000";--定义内部信号s1
signal count1:integer range 1 downto 0;
signal firstv:integer range 0 downto 1;
signal codeoutb:std_logic_vector(1 downto 0);
signal flagv:integer range 1 downto 0;
signal D1,D0:std_logic_vector(3 downto 0);
signal code_out1:std_logic_vector(1 downto 0);
signal t:std_logic_vector(1 downto 0);
component dff
port(d:in std_logic;
clk:in std_logic;
q:out std_logic);
end component;
begin
code_out1<=t;
process (clk,t) is
begin
if (clk='1' and clk'event) then
if ((code_out1="11" and D1(3 downto 0)="0001" and D0(3 downto 0)="0001")or
(code_out1="01" and D1(3 downto 0)="0000" and D0(3 downto 0)="0001"))then
D1(2 downto 1)<=D1(3 downto 2);
D0(2 downto 1)<=D0(3 downto 2);
D1(3)<='0';
D0(3)<='0';
D1(0)<=D1(1);
D0(0)<=D0(1);
elsif((code_out1="11" and D1(3 downto 1)="001" and D0(3 downto 1)="001")or
(code_out1="01" and D1(3 downto 1)="000" and D0(3 downto 1)="001")) then
D1(2 downto 1)<=D1(3 downto 2);
D0(2 downto 1)<=D0(3 downto 2);
D1(3)<='0';
D0(3)<='0';
D1(0)<='0';
D0(0)<='0';
else
D1(2 downto 1)<=D1(3 downto 2);
D0(2 downto 1)<=D0(3 downto 2);
D1(3)<=t(1);
D0(3)<=t(0);
D1(0)<=D1(1);
D0(0)<=D0(1);
end if;
end if;
end process;
process(clk)is
begin
if (clk='1' and clk'event)then
if((D1(0)='1' and D0(0)='1')or(D1(0)='0' and D0(0)='1')) then
code_out<='1';------------检测+1,-1,输出1码
else code_out<='0';----输出0码
end if;
end if;
end process;
end;