eetop.cn_vhdl语言例程集锦(精品).rar_VHDL例程_vhdl

Advanced Electronic Design Automation

Examples of VHDL Descriptions

Author: Ian Elliott of Northumbria University

This file contains a selection of VHDL source files which serve to illustrate the diversity and power of the language when used to describe various types of hardware. The examples range from simple combinational logic, described in

● Memory

● State Machines

● Registers

● Systems

● ADC and DAC

● Arithmetic

Combinational Logic

● Exclusive-OR Gate (Dataflow style)

● Exclusive-OR Gate (Behavioural style)

● Exclusive-OR Gate (Structural style)

● Octal Bus Transceiver

● Quad 2-input OR

● 8-bit Identity Comparator

● Hamming Encoder

● Hamming Decoder

● 2-to-4 Decoder with Testbench and Configuration

● Multiplexer 16-to-4 using Selected Signal Assignment Statement

● Multiplexer 16-to-4 using Conditional Signal Assignment Statement

● Multiplexer 16-to-4 using if-then-elsif-else Statement

● M68008 Address Decoder

● Counter using Multiple Wait Statements

● Synchronous Down Counter with Parallel Load

● Mod-16 Counter using JK Flip-flops

● Pseudo Random Bit Sequence Generator

● Universal Counter/Register

● n-Bit Synchronous Counter

Shift Registers

● Universal Shift Register/Counter

● TTL164 Shift Register

● Behavioural description of an 8-bit Shift Register

State Machines

● Classic 2-Process State Machine and Test Bench

● State Machine using Variable

● State Machine with Asynchronous Reset

● Pattern Detector FSM with Test Bench

● State Machine with Moore and Mealy outputs

● Moore State Machine with Explicit State encoding

● Mealy State Machine with Registered Outputs

● Moore State Machine with Concurrent Output Logic

Systems

ADC and DAC

● Package defining a Basic Analogue type

● 16-bit Analogue to Digital Converter

● 16-bit Digital to Analogue Converter

● 8-bit Analogue to Digital Converter

● 8-bit Unipolar Successive Approximation ADC

Arithmetic

● 8-bit Unsigned Multiplier

● n-bit Adder using the Generate Statement

● A Variety of Adder Styles

Universal Register

Description - This design is a universal register which can be used as a straightforward storage register, a bi-directional shift register, an up counter and a down counter. The register can be loaded from a set of parallel data inputs

and the mode is controlled by a 3-bit input. The 'termcnt' (terminal count) output goes high when the register contains zero.

LIBRARY ieee;

USE ieee.Std_logic_1164.ALL;

USE ieee.Std_logic_unsigned.ALL;

ENTITY unicntr IS

GENERIC(n : Positive := 8); --size of counter/shifter

PORT(clock, serinl, serinr : IN Std_logic; --serial inputs

mode : IN Std_logic_vector(2 DOWNTO 0); --mode control

BEGIN

main_proc : PROCESS

BEGIN

WAIT UNTIL rising_edge(clock);

CASE mode IS

--reset

WHEN "000" => int_reg <= (OTHERS => '0');

--parallel load

WHEN "001" => int_reg <= datain;

--count up

WHEN "101" => int_reg <= serinr & int_reg((n-1) DOWNTO 1);

--do nothing

WHEN OTHERS => NULL;

END CASE;

END PROCESS;

det_zero : PROCESS(int_reg) --detects when count is 0

BEGIN

termcnt <= '1';

FOR i IN int_reg'Range LOOP

IF int_reg(i) = '1' THEN

dataout <= int_reg;

END v1;

Octal D-Type Register with 3-State Outputs

Simple model of an Octal D-type register with three-state outputs using two concurrent statements.

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY ttl374 IS

PORT(clock, oebar : IN std_logic;

data : IN std_logic_vector(7 DOWNTO 0);

qout : OUT std_logic_vector(7 DOWNTO 0));

begin

Exclusive-OR Gate (Structural style)