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tessent edt dft手册 eetop.cn_edt_gd.pdf
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Tessent EDT DFT 手册
Tessent EDT DFT 手册是 Mentor Graphics Corporation 发布的一份关于 Tessent TestKompress 的用户手册,该手册旨在帮助用户快速了解和掌握 Tessent TestKompress 的使用方法和技术细节。
Tessent EDT DFT 手册中包含了大量关于 Tessent TestKompress 的知识点,包括软件安装、配置、测试方法、故障诊断等方面的内容。在本手册中,用户可以找到关于 Tessent TestKompress 的详细介绍、操作指南、故障诊断方法等信息。
Tessent EDT DFT 手册的主要内容包括:
1. Tessent TestKompress 介绍
Tessent TestKompress 是一种基于压缩技术的测试数据压缩工具,该工具可以将测试数据压缩到最小,减少测试时间和成本。在本手册中,用户可以找到关于 Tessent TestKompress 的详细介绍、特点、优势等信息。
2. 软件安装和配置
本手册中提供了详细的软件安装和配置指南,包括安装环境、软件 requirements、配置选项等信息。用户可以根据实际情况选择适合的安装和配置方法。
3. 测试方法
Tessent TestKompress 提供了多种测试方法,包括压缩测试、解压缩测试、 fault diagnosis 等。在本手册中,用户可以找到关于这些测试方法的详细介绍和操作指南。
4. 故障诊断
Tessent TestKompress 提供了强大的故障诊断功能,用户可以根据实际情况选择适合的故障诊断方法。在本手册中,用户可以找到关于故障诊断的详细介绍和操作指南。
5. 技术支持
本手册中提供了详细的技术支持信息,包括常见问题解答、技术支持资源、错误代码解释等信息。用户可以根据实际情况选择适合的技术支持方法。
Tessent EDT DFT 手册是一份非常有价值的资源,对于 Tessent TestKompress 的用户非常有帮助。本手册为用户提供了详细的操作指南、技术细节和故障诊断方法等信息,帮助用户快速掌握 Tessent TestKompress 的使用方法和技术细节。
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Tessent
®
TestKompress
®
User’s Manual
Software Version 2015.2
© 2001-2015 Mentor Graphics Corporation
All rights reserved.
This document contains information that is proprietary to Mentor Graphics Corporation. The original recipient of this
document may duplicate this document in whole or in part for internal business purposes only, provided that this entire
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Tessent TestKompress User’s Manual, v2015.2, 9.2
3
Table of Contents
Chapter 1
Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Tessent TestKompress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
EDT Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Scan Channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Structure and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TestKompress Compression Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TestKompress Usage Flow Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
EDT IP Creation and Pattern Generation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Pre-Synthesis Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Tessent Core Description (TCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
EDT IP Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
EDT Logic Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
EDT Pattern Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Tessent Shell User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Chapter 2
The Compressed Pattern Flows. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Top-Down Design Flows. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
The Compressed Pattern Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Design Requirements for a Compressed Pattern Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Compressed Pattern External Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Compressed Pattern Internal Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Chapter 3
Scan Chain Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Design Preparation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Scan Chain Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
ATPG Baseline Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Chapter 4
Test Points for Pattern Count Reduction or Improving Test Coverage . . . . . . . . . . . . . . 53
EDT Test Points for Reducing Pattern Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
How to Specify Test Point Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
How to Analyze and Insert Test Points in a Pre-Scan Design . . . . . . . . . . . . . . . . . . . . . . 55
How to Analyze and Insert Test Points in a Post-Scan Design . . . . . . . . . . . . . . . . . . . . . 57
How to Insert Test Points and Do Scan Stitching Using Third-Party Tools . . . . . . . . . . . 59
Static Timing Analysis for EDT Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
User-Defined Test Points Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
How to Prevent Test Points on Multi-Cycle Paths, False Paths and Critical Paths. . . . . . . . 61
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Table of Contents
4
Tessent TestKompress User’s Manual, v2015.2, 9.2
Test Point Analysis to Improve Test Coverage for Deterministic Patterns. . . . . . . . . . . . . . 62
Targeted Test Faults Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
How to Use Test Points for Pattern Count Reduction and Improving Test Coverage . . . . . 64
How to Insert both EDT and LogicBIST Test Points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Chapter 5
Creation of the EDT Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Compression Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Analyzing Compression. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Preparation for EDT Logic Creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Parameter Specification for the EDT Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Dual Compression Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Defining Dual Compression Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Asymmetric Input and Output Channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Bypass Scan Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Latch-Based EDT logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Compactor Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Pipeline Stages in the Compactor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Pipeline Stages Added to the Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Longest Scan Chain Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
EDT Logic Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
EDT Architecture Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Specifying Hard Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Pulse EDT Clock Before Scan Shift Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Reporting of the EDT Logic Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
EDT Control and Channel Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Functional/EDT Pin Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Shared Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Connections for EDT Pins (Internal Flow only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Internally Driven EDT Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Structure of the Bypass Chains. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Decompressor and Compactor Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
IJTAG and the EDT IP TCD Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Design Rule Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Creation of EDT Logic Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
The EDT Logic Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
IJTAG and EDT Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Specification of Module/Instance Names. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
EDT Logic Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Inserting EDT Logic During Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Synthesis Script that Inserts/Synthesizes EDT Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Creation of a Reduced Netlist for Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Chapter 6
Synthesizing the EDT Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
The EDT Logic Synthesis Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Synthesis and External EDT Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Synthesis and Internal EDT Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
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Table of Contents
Tessent TestKompress User’s Manual, v2015.2, 9.2
5
SDC Timing File Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
EDT Logic/Core Interface Timing Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Scan Chain and ATPG Timing Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Chapter 7
Generating/Verifying Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Preparation for Test Pattern Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
EDT Pattern Generation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
IJTAG Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Scan Chain Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
EDT Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Used Input Channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Updating Scan Pins for Test Pattern Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Verification of the EDT Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Design Rules Checking (DRC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
EDT Logic and Chain Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Reducing Serial EDT Chain Test Simulation Runtime . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Test Pattern Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Generating Patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Compression Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Saving of the Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Post-Processing of EDT Patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Simulation of the Generated Test Patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Chapter 8
Modular Compressed ATPG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
The Modular Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Understanding Modular Compressed ATPG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Development of a Block-Level Compression Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Balancing Scan Chains Between Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Sharing Input Scan Channels on Identical EDT Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Channel Sharing for Non-Identical EDT Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Mixing Channel Sharing for Non-Identical EDT Blocks and Channel Broadcasting for
Identical EDT Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Generating Modular EDT Logic for a Fully Integrated Design . . . . . . . . . . . . . . . . . . . . . 167
Estimating Test Coverage/Pattern Count for EDT Blocks . . . . . . . . . . . . . . . . . . . . . . . . . 168
Legacy ATPG Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Generation of Top-level Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Chapter 9
Special Topics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Low-Power Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Low-Power Shift. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Setting Up Low-Power Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Low Pin Count Test Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
LPCT Controller Decision Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
LPCT Controller Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
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