ram.rar_ram_ram verilog_ram veril_verilog ram_双端口ram

/**************************************************** * File: d64x16.v * Description: This is a synchronous dual-port * memory model, 64 words by 16-bit wide ****************************************************/ module d64x16 (wclk, waddr, wrdata, wrena, rclk, raddr, rddata); input wclk, // write clock wrena, // write enable rclk; // read clock to latch the address input[5:0] waddr, // write address raddr; // read address input[15:0] wrdata; // write data output[15:0] rddata; // read data output reg[5:0] braddr; // buffered read address reg[15:0] mem[0:63]; // memory reg[6:0] i; // loop variable wire wvalid = (^waddr)===1'b0 || (^waddr)===1'b1, rvalid = (^braddr)===1'b0 || (^braddr)===1'b1; always @(posedge wclk) begin if(wrena===1'b1 && wvalid) mem[waddr] = wrdata; // valid write condition else if(wrena!==1'b0 && wvalid) // X enable mem[waddr] = ((mem[waddr]^wrdata) & 16'bx) ^ mem[waddr]; else if(wrena!==1'b0 && !wvalid) begin // invalid write address for(i=0;i<64;i=i+1) begin // write all possible address with possible bad data if((&(waddr^i[5:0]))===1'b0 && (|(waddr^i[5:0]))!==1'b1) // match mem[i] = ((mem[i]^wrdata) & 16'bx) ^ mem[i]; end end if(wrena===1'bx) $display($stime,,"[%m] Warning: Memory is driven by wrena=X."); if(wrena!==1'b0 && !wvalid) $display($stime,,"[%m] Warning: Memory is written with invalid address."); end always begin @(wclk); // do not reprint message until next change if(wclk===1'bx) $display($stime,,"[%m] Warning: write clock is unknown."); end always @(posedge rclk) braddr <= raddr; assign rddata = mem[braddr]; endmodule