/*wisard ARM for keil ver 1.01(Alfa)
Provided By AriaSanat Group*/
/*********************************************************
Project Name:
Date: 2011/05/25
Author:
Company: AriaSanat
Version:
Description:
*********************************************************/
#include <lpc23xx.h>
#include "type.h"
#include "usart.h"
//#include "irq.h"
#define I_Bit 0x80
#define F_Bit 0x40
#define SYS32Mode 0x1F
#define IRQ32Mode 0x12
#define FIQ32Mode 0x11
static DWORD sysreg; /* used as LR register */
#define IENABLE __asm { MRS sysreg, SPSR; MSR CPSR_c, #SYS32Mode }
#define IDISABLE __asm { MSR CPSR_c, #(0x12|0x80); MSR SPSR_cxsf, sysreg }
/* Usart0 Interrupt Rutine */
__irq void usart0_handler()
{
//Place Your Code Here
VICVectAddr=0x0;
}
/* Usart1 Interrupt Rutine */
__irq void usart1_handler()
{ static char i;
if(i){FIO0SET=0xff,i=0;}
else {FIO0CLR=0xff,i=1;}
//Place Your Code Here
// printf("u_irq1");
//U0IIR=0x4;
IDISABLE;
VICVectAddr=0x0;
}
/* Usart2 Interrupt Rutine */
__irq void usart2_handler()
{
// Place Your Code Here
VICVectAddr=0;
}
/* Usart3Interrupt Rutine */
__irq void usart3_handler()
{
//Place Your Code Here
VICVectAddr=0;
}
int main(void)
{
char ch;
SCS |=0x1; // Access To Fast GPIO 0,1
/* configuration PORT 0 */
PINSEL0 =0x0;
PINSEL1 =0x0;
//--------------------------
FIO0DIR=0x0; //direct PORT 0
// Active BITs :
//---------------------------------------
FIO0SET=0x0; //set PORT 0
// Active BITs :
//---------------------------------------
FIO0MASK=0x0; //mask PORT 0
// Active BITs :
//---------------------------------------
PINMODE0=0x0; //pullup PORT 0
// Active BITs :
//---------------------------------------
/* configuration PORT 1 */
PINSEL2 =0x0;
PINSEL3 =0x0;
//-------------------------
FIO1DIR=0x0; //direct PORT 1
// Active BITs :
//---------------------------------------
FIO1SET=0x0; //set PORT 1
// Active BITs :
//---------------------------------------
FIO1MASK=0x0; //mask PORT 1
// Active BITs :
//---------------------------------------
PINMODE1=0x0; //pullup PORT 1
// Active BITs :
//---------------------------------------
usart0_init(0x4,0x0,0x85); // Pclk: 12.000MHz BaudRate : 115200 bit/sec Error : 0.16%
/* init Usart0 Interrupt */
U0IER=0x1;
VICVectAddr4=(unsigned long)usart0_handler;
VICIntEnable=1<<6;
//---------------------------------------
usart1_init(0x4,0x0,0x85); // Pclk: 12.000MHz BaudRate : 115200 bit/sec Error : 0.16%
/* init Usart1 Interrupt */
U1IER=0x3;
VICVectAddr7=(unsigned long)usart1_handler;
VICIntEnable=1<<7;
//---------------------------------------
usart2_init(0x4,0x0,0x85); // Pclk: 12.000MHz BaudRate : 115200 bit/sec Error : 0.16%
/* init Usart2 Interrupt */
U2IER=0x2;
VICVectAddr28=(unsigned long)usart2_handler;
VICIntEnable=1<<28;
//---------------------------------------
usart3_init(0x4,0x0,0x85); // Pclk: 12.000MHz BaudRate : 115200 bit/sec Error : 0.16%
/* init Usart3 Interrupt */
U3IER=0x2;
VICVectAddr29=(unsigned long)usart3_handler;
VICIntEnable=1<<29;
//---------------------------------------
while (1)
{
// PlaceYour Code Here
printf("main\n");
//scanf("%c",&ch);
} //while
} //main
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