vhdl.rar_VHDL 输入输出

-- Quartus VHDL Template -- Clearable loadable enablable counter LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY s IS PORT ( A,B : IN STD_LOGIC_VECTOR(7 DOWNTO 0); IE,OE : IN STD_LOGIC; Ci : IN STD_LOGIC; S : IN STD_LOGIC_VECTOR(2 DOWNTO 0); Co : OUT STD_LOGIC; Y : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END s; ARCHITECTURE ting OF s IS SIGNAL he: STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL C1: STD_LOGIC_VECTOR(8 DOWNTO 0); SIGNAL Ca: STD_LOGIC_VECTOR(8 DOWNTO 0); SIGNAL Cb: STD_LOGIC_VECTOR(8 DOWNTO 0); SIGNAL Sa: STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL Sb: STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL i1: STD_LOGIC; SIGNAL i2: STD_LOGIC; SIGNAL A1: STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL B1: STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL C: STD_LOGIC; BEGIN PROCESS (A,B,Ci,IE) BEGIN if(IE'event and IE='1')then A1<=A; B1<=B; C<=Ci; end if; end process; PROCESS (A1,B1,C) BEGIN C1(1)<=C; for i1 IN 0 TO 7 LOOP C1(i1+1)<=((A(i1)and B(i1)) or (C1(i1)and B(i1))or (A(i1)and C1(i1))); he(i1)<=(A(i1) xor B(i1) xor C1(i1)); end loop; if(C='0')then Sa<=A; Sb<=B; Ca(8)<='0'; Cb(8)<='0'; else Ca(1)<='1'; for i2 IN 0 TO 7 LOOP Sa(i2)<=(A(i2) xor Ca(i2)); Ca(i2+1)<=(A(i2) and Ca(i2)); Sb(i2)<=(B(i2) xor Cb(i2)); Cb(i2+1)<=(B(i2) and Cb(i2)); end loop; end if; end process; PROCESS (OE,S) BEGIN if(OE='0')then if(S="000")then Y<=he; co<=C1(8); end if; if(S="001")then if(C='0')then Y<=A1-B1; else Y<=A1-B1-"00000001"; end if; end if; if(S="010")then Y<=A1 and B1; end if; if(S="011")then Y<=A1 or B1; end if; if(S="100")then Y<=not(A1 and B1); end if; if(S="101")then Y<=not(A1 or B1); end if; if(S="110")then Y<=Sa; co<=Ca(8); end if; if(S="111")then Y<=Sb; co<=Cb(8); end if; else Y<="ZZZZZZZZ"; end if; END PROCESS; END ting;