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TMS320C6701

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SPRS067F − MAY 1998 − REVISED MARCH 2004

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

D Highest Performance Floating-Point Digital

Signal Processor (DSP) TMS320C6701

− 8.3-, 6.7-, 6-ns Instruction Cycle Time

− 120-, 150-, 167-MHz Clock Rate

− Eight 32-Bit Instructions/Cycle

− 1 GFLOPS

− TMS320C6201 Fixed-Point DSP

Pin-Compatible

D VelociTI Advanced Very Long Instruction

Word (VLIW) C67x CPU Core

− Eight Highly Independent Functional

Units:

− Four ALUs (Floating- and Fixed-Point)

− Two ALUs (Fixed-Point)

− Two Multipliers (Floating- and

Fixed-Point)

− Load-Store Architecture With 32 32-Bit

General-Purpose Registers

− Instruction Packing Reduces Code Size

− All Instructions Conditional

D Instruction Set Features

− Hardware Support for IEEE

Single-Precision Instructions

− Hardware Support for IEEE

Double-Precision Instructions

− Byte-Addressable (8-, 16-, 32-Bit Data)

− 8-Bit Overflow Protection

− Saturation

− Bit-Field Extract, Set, Clear

− Bit-Counting

− Normalization

D 1M-Bit On-Chip SRAM

− 512K-Bit Internal Program/Cache

(16K 32-Bit Instructions)

− 512K-Bit Dual-Access Internal Data

(64K Bytes)

D 32-Bit External Memory Interface (EMIF)

− Glueless Interface to Synchronous

Memories: SDRAM and SBSRAM

− Glueless Interface to Asynchronous

Memories: SRAM and EPROM

− 52M-Byte Addressable External Memory

Space

D Four-Channel Bootloading

Direct-Memory-Access (DMA) Controller

With an Auxiliary Channel

D 16-Bit Host-Port Interface (HPI)

− Access to Entire Memory Map

D Two Multichannel Buffered Serial Ports

(McBSPs)

− Direct Interface to T1/E1, MVIP, SCSA

Framers

− ST-Bus-Switching Compatible

− Up to 256 Channels Each

− AC97-Compatible

− Serial-Peripheral-Interface (SPI)

Compatible (Motorola)

D Two 32-Bit General-Purpose Timers

D Flexible Phase-Locked-Loop (PLL) Clock

Generator

D IEEE-1149.1 (JTAG

†

)

Boundary-Scan-Compatible

D 352-Pin Ball Grid Array (BGA) Package

(GJC Suffix)

D 0.18-µm/5-Level Metal Process

− CMOS Technology

D 3.3-V I/Os, 1.8-V Internal (120-, 150-MHz)

D 3.3-V I/Os, 1.9-V Internal (167-MHz Only)

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

126

GJC (352-PIN BGA) PACKAGE

( BOTTOM VIEW )

VelociTI is a trademark of Texas Instruments.

Motorola is a trademark of Motorola, Inc.

†

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

TMS320C6701

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SPRS067F − MAY 1998 − REVISED MARCH 2004

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Table of Contents

parameter measurement information 31. . . . . . . . . . . . . . .

signal-transition levels 31. . . . . . . . . . . . . . . . . . . . . . . . . . . .

input and output clocks 32. . . . . . . . . . . . . . . . . . . . . . . . . . .

asynchronous memory timing 35. . . . . . . . . . . . . . . . . . . . .

synchronous-burst memory timing 37. . . . . . . . . . . . . . . . .

synchronous DRAM timing 41. . . . . . . . . . . . . . . . . . . . . . . .

HOLD

/HOLDA timing 45. . . . . . . . . . . . . . . . . . . . . . . . . . . .

reset timing 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

external interrupt timing 48. . . . . . . . . . . . . . . . . . . . . . . . . .

host-port interface timing 49. . . . . . . . . . . . . . . . . . . . . . . . .

multichannel buffered serial port timing 52. . . . . . . . . . . . .

DMAC, timer, power-down timing 63. . . . . . . . . . . . . . . . . .

JTAG test-port timing 65. . . . . . . . . . . . . . . . . . . . . . . . . . . .

mechanical data 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

revision history 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GJC BGA package (bottom view) 1. . . . . . . . . . . . . . . . . . . . . .

description 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

device characteristics 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

functional block and CPU diagram 4. . . . . . . . . . . . . . . . . . . . .

CPU description 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

signal groups description 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

signal descriptions 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

development support 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

documentation support 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

clock PLL 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

power-down logic mode 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

absolute maximum ratings over operating case

temperature range 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

recommended operating conditions 29. . . . . . . . . . . . . . . . . . .

electrical characteristics over recommended ranges of

supply voltage and operating case temperature 30. . . .

description

The TMS320C67x DSPs are the floating-point DSP family in the TMS320C6000 DSP platform. The

TMS320C6701 (C6701) device is based on the high-performance, advanced VelociTI

very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an

excellent choice for multichannel and multifunction applications. With performance of up to 1 giga floating-point

operations per second (GFLOPS) at a clock rate of 167 MHz, the C6701 offers cost-effective solutions to

high-performance DSP programming challenges. The C6701 DSP possesses the operational flexibility of

high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose

registers of 32-bit word length and eight highly independent functional units. The eight functional units provide

four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The C6701 can

produce two multiply-accumulates (MACs) per cycle for a total of 334 million MACs per second (MMACS). The

C6701 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program

memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space.

Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered

serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory

interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.

The C6701 has a complete set of development tools which includes: a new C compiler, an assembly optimizer

to simplify programming and scheduling, and a Windows debugger interface for visibility into source code

execution.

TMS320C6000 is a trademark of Texas Instruments.

Windows is a registered trademark of Microsoft Corporation.

TMS320C6701

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SPRS067F − MAY 1998 − REVISED MARCH 2004

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

device characteristics

Table 1 provides an overview of the C6701 DSP. The table shows significant features of each device, including

the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count, etc.

Table 1. Characteristics of the C6701 Processors

HARDWARE FEATURES C6701

EMIF 1

DMA 4-Channel

Peripherals

Host-Port Interface (HPI) 1

Peripherals

McBSPs 2

32-Bit Timers 2

Internal Program Memory

Size (Bytes) 64K

Internal Program Memory

Organization 64K Bytes Cache/Mapped Program

Internal Data Memory

Size (Bytes) 64K

Internal Data Memory

Organization

2 Blocks: Eight 16-Bit Banks per Block 50/50 Split

Frequency MHz 120, 150, 167

Cycle Time ns 6 ns (6701-167); 6.7 ns (6701-150); 8.3 ns (6701-120)

Core (V)

1.8 (6701-120, -150)

Voltage

Core (V)

1.9 (6701-167 only)

Voltage

I/O (V) 3.3

PLL Options CLKIN frequency multiplier Bypass (x1), x4

BGA Package 35 × 35 mm 352-pin GJC

Process Technology µm 0.18 µm

Product Status

Product Preview (PP)

Advance Information (AI)

Production Data (PD)

TMS320C6701

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SPRS067F − MAY 1998 − REVISED MARCH 2004

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

functional block and CPU diagram

Program

Control

Logic

Test

C67x CPU

Data Path B

B Register File

Program

Access/Cache

Controller

Instruction Fetch

Instruction Dispatch

Instruction Decode

Data Path A

A Register File

Data

Access

Controller

Power-

Down

Logic

.L1

†

.S1

†

.M1

†

.D1 .D2 .M2

†

.S2

†

.L2

†

ROM/FLASH

SRAM

I/O Devices

Timer 0

Timer 1

External Memory

Interface (EMIF)

Multichannel

Buffered Serial

Port 0

Multichannel

Buffered Serial

Port 1

Direct Memory

Access Controller

(DMA)

(4 Channels)

Host Port

Interface

(HPI)

Internal Program Memory

1 Block Program/Cache

(64K Bytes)

Control

Registers

Internal Data

Memory

(64K Bytes)

2 Blocks of 8 Banks

Each

In-Circuit

Emulation

Interrupt

Control

Framing Chips:

H.100, MVIP,

SCSA, T1, E1

AC97 Devices,

SPI Devices,

Codecs

DMA Buses

Data Bus

C6701 Digital Signal Processor

PLL

(x1, x4)

Bus

SBSRAM

SDRAM

HOST CONNECTION

MC68360 Glueless

MPC860 Glueless

PCI9050 Bridge + Inverter

MC68302 + PAL

MPC750 + PAL

MPC960 (Jx/Rx) + PAL

†

These functional units execute floating-point instructions.

TMS320C6701

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SPRS067F − MAY 1998 − REVISED MARCH 2004

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

CPU description

The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight

32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features

controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The

first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the

previous instruction, or whether it should be executed in the following clock as a part of the next execute packet.

Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length

execute packets are a key memory-saving feature, distinguishing the C67x CPU from other VLIW architectures.

The CPU features two sets of functional units. Each set contains four units and a register file. One set contains

functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files

contain 16 32-bit registers each for the total of 32 general-purpose registers. The two sets of functional units,

along with two register files, compose sides A and B of the CPU (see the Functional and CPU Block diagram

and Figure 1). The four functional units on each side of the CPU can freely share the 16 registers belonging to

that side. Additionally, each side features a single data bus connected to all registers on the other side, by which

the two sets of functional units can access data from the register files on opposite sides. While register access

by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle,

The C67x CPU executes all TMS320C62x DSP fixed-point instructions. In addition to the C62x DSP

fixed-point instructions, the six out of eight functional units (.L1, .M1, .D1, .D2, .M2, and .L2) also execute

floating-point instructions. The remaining two functional units (.S1 and .S2) also execute the new LDDW

instruction which loads 64 bits per CPU side for a total of 128 bits per cycle.

Another key feature of the C67x CPU is the load/store architecture, where all instructions operate on registers

(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data

transfers between the register files and the memory. The data address driven by the .D units allows data

addresses generated from one register file to be used to load or store data to or from the other register file. The

C67x CPU supports a variety of indirect-addressing modes using either linear- or circular-addressing modes

with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some

registers, however, are singled out to support specific addressing or to hold the condition for conditional

instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies.

The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results

available every clock cycle.

The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.

The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least

significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous

execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,

effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the

fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of

the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet

can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one

per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch

packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units

for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit

registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store

instructions are byte-, half-word, or word-addressable.

TMS320C62x is a trademark of Texas Instruments.

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2023-01-12

去TI官网下载吧，我看错了晕了，按错按钮了，竟然点了下载

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