module gyy(k6,k7,k8,led5,led6,led7,led8,k,led,clk,g1,g2,g3,g4,g5);
input k6,k7,k8;
input [4:1]k;
input clk;
output led5,led6,led7,led8;
output [5:2]led;
output [7:0]g1;
output [7:0]g2;
output [7:0]g3;
output [7:0]g4;
output [7:0]g5;
reg led5,led6,led7,led8;
reg [7:0]g1;
reg [7:0]g2;
reg [7:0]g3;
reg [7:0]g4;
reg [7:0]g5;
reg [4:1]led;
reg block;
reg [7:0]g0;
reg [3:0]num1;
reg [3:0]num2;
reg [3:0]num3;
reg [3:0]num4;
reg [3:0]num5;
reg [20:1]count1,count2;
reg fen1,fen2;
initial begin
num1='d10;
end
always @(posedge clk)
begin if(count1==20'd2000)begin
fen1<=~fen1;count1<=0;end
else begin count1<=count1+1'b1;
end
end
always @(posedge fen1)
begin if(count2=='d500)begin
fen2<=~fen2;count2<=0;end
else begin count2<=count2+1'b1;
end
end
