PWM-TEST.zip_dsPIC33FJ16GS504_pwm

#include <p33FJ16GS504.h> // Configuration bits _FOSCSEL(FNOSC_FRC) _FOSC(FCKSM_CSECMD & OSCIOFNC_ON & IOL1WAY_OFF) _FWDT(FWDTEN_OFF) _FPOR(FPWRT_PWR128) _FICD(ICS_PGD2 & JTAGEN_OFF) int main(void) { // Configure Oscillator to operate the device at 40 MIPS // Fosc = Fin*M/(N1*N2), Fcy = Fosc/2 // Fosc = 7.37*(43)/(2*2) = 80MHz for Fosc, Fcy = 40MHz // Configure PLL prescaler, PLL postscaler, PLL divisor PLLFBD = 41; // M = PLLFBD + 2 CLKDIVbits.PLLPOST = 0; // N1 = 2 CLKDIVbits.PLLPRE = 0; // N2 = 2 // Change oscillator to FRC + PLL __builtin_write_OSCCONH(0x01); // New Oscillator FRC w/ PLL __builtin_write_OSCCONL(0x01); // Enable Clock Switch while(OSCCONbits.COSC != 0b001); // Wait for new Oscillator to become FRC w/ PLL while(OSCCONbits.LOCK != 1); // Wait for Pll to Lock // Now setup the ADC and PWM clock for 120MHz // ((FRC * 16) / APSTSCLR ) = (7.37 * 16) / 1 = ~ 120MHz ACLKCONbits.FRCSEL = 1; // FRC provides input for Auxiliary PLL (x16) ACLKCONbits.SELACLK = 1; // Auxiliary Ocillator provides clock source for PWM & ADC ACLKCONbits.APSTSCLR = 7; // Divide Auxiliary clock by 1 ACLKCONbits.ENAPLL = 1; // Enable Auxiliary PLL while(ACLKCONbits.APLLCK != 1); // Wait for Aux. PLL to Lock TRISAbits.TRISA4 = 0; // GPIO setup for override of PWM1 TRISAbits.TRISA3 = 0; LATAbits.LATA4 = 0; LATAbits.LATA3 = 0; TRISBbits.TRISB13 = 0; // GPIO setup for override of PWM2 TRISBbits.TRISB14 = 0; LATBbits.LATB13 = 0; LATBbits.LATB14 = 0; TRISBbits.TRISB11 = 0; // GPIO setup for override of PWM3 TRISBbits.TRISB12 = 0; LATBbits.LATB11 = 0; LATBbits.LATB12 = 0; // PWM setup for Interleaved Flyback Inverter primary section PTPER = 4808; // Flyback inverter period value PHASE2 = 2404; // 180Deg phase-shift for second converter PTCONbits.PTEN = 1; PTCON2bits.PCLKDIV = 3; // Maximum (1.04nsec) timing resolution PWMCON1bits.ITB = 0; // PTPER register provides the timing for PWM1, PWM2 generator PWMCON2bits.ITB = 0; PWMCON1bits.IUE = 1; // Enable immediate updates PWMCON2bits.IUE = 1; PWMCON1bits.DTC = 0; // Positive dead-time enabled PWMCON2bits.DTC = 0; //CSM // Workaround for Errata #32 IOCON1bits.PENH = 1; // PWM controls PWM pins @ test IOCON1bits.PENL = 1; IOCON2bits.PENH = 1; IOCON2bits.PENL = 1; IOCON1bits.PMOD = 0; // PWM1H and PWM1L is in complementary output mode IOCON2bits.PMOD = 0; // PWM2H and PWM2L is in complementary output mode IOCON1bits.OVRENH = 0; //PWM Master the i/o pin IOCON1bits.OVRENL = 0; //PWM Master the i/o pin IOCON2bits.OVRENH = 0; //PWM Master the i/o pin IOCON2bits.OVRENL = 0; //PWM Master the i/o pin ALTDTR1 = 175; // Setup dead-time DTR1 = 175; ALTDTR2 = 175; DTR2 = 175; PDC1 = 2404; // Initialize Flyback duty cycle PDC2 = 2404; TRGCON2bits.TRGDIV = 0; // Trigger every 2nd PWM Period ~17us 0 FOR 57KHZ TRGCON2bits.TRGSTRT = 0; // Wait 0 PWM cycles before generating first PWM trigger TRIG1 = 1000; // PWM1 used to trigger ADCP0 TRIG2 = 1000; // Initialize PWM3 for SCR bridge PWMCON3bits.ITB = 0; // MASTER time base for PWM3 PWMCON3bits.IUE = 1; // Enable immediate updates IOCON3bits.PENH = 0; // GPIO controls the PWM3H pin @ startup IOCON3bits.PENL = 0; IOCON3bits.PMOD = 3; // True independent output Mode IOCON3bits.OVRDAT = 0; // SCR will be turned off at start-up IOCON3bits.OVRENH = 1; // Enable the over ride at startup IOCON3bits.OVRENL = 1; // Enable the over ride at startup PDC3 = 0; SDC3 = 0; while(1) { Nop(); Nop(); Nop(); } }