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Static Timing Analysis
Techniques for FPGAs
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Static Timing Analysis
Techniques for FPGAs
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Why STA?
• Verify the design meets timing constraints
• Faster than timing-driven, gate-level simulation
• Ease design debugging
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Timing In FPGAs
LatticeECP2/M Slice Diagram
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Agenda
• Introduction to Static Timing Analysis
• Elements of Timing Verification
• Timing in FPGAs
• Analysis Examples
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Overview
• Design Flow
• Dynamic Versus Static Simulation
• Key Definitions
– Critical Path
– Arrival Time
– Required Time
– Slack
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Design Flow
New
Design
RTL
Development
Synthesis
Place & Route
Program
Device
Design
Complete
Post-PAR
STA
Post-Synthesis
STA
Timing
Simulation
Functional
Simulation
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Dynamic Versus Static Verification
9Ex: Lattice Semiconductor trace programEx: Mentor Graphics ModelSim
9 Checks every path for timing violationsDifficult to cover all paths
9 Min/Max, clock skew, exceptionsSimple timing checks
9 Synchronous designs onlySupports asynchronous designs
9 Confirms timing onlyConfirms function and timing
9 Typical runtime is fastTypically time and compute intensive
StaticDynamic
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STA Compute Method
