library ieee;
use ieee.std_logic_1164.all;
entity miaobiao is
port(ain,bin,cin,hin:in std_logic;
p1,p2,p3,p4,p5,p6,p7,s1,s0:out std_logic);
end miaobiao;
architecture one of miaobiao is
component cdu_50
port(clk:in std_logic;
y: out std_logic);
end component;
component cdu_100
port(clk:in std_logic;
clk2:out std_logic);
end component;
component xiaodou
port(clk,d_in:in std_logic;
d_out:out std_logic);
end component;
component cdu49
port(star_stop,clk,rst:in std_logic;
cout:out std_logic;
q:out std_logic_vector(7 downto 0));
end component;
component cdu60
port(star_stop,clk,rst:in std_logic;
q:out std_logic_vector(7 downto 0));
end component;
component disp
port(a3,a2,a1,a0:in std_logic;
dout:out std_logic_vector(6 downto 0));
end component;
component mux21a
port(d1,d0,a0:in std_logic;
