1FRI 滤波器的 HDL 实现
()l 顶层模块的硬件描述语言(verligo)实现
Module Basie_RI(
elok,//时钟
reset,//异步复位信号
clk_ena,//时钟使能信号
data_in,//输入数据(18 位)
fir_result//输出数据(38 位)
);
iPnut clock;
input reset;
iPnut clk_ena;
iPnut [17:0]data_in;
output [37:0]fir_resutl;
wire [17:0]coeff_0;
wire [17:0] coeff_1:
wire [17:0] coeff_2;
wire [17:0] coeff_3;
wire [17:0] coeff_4;
wire [17:0] coeff_5:
wire [17:0] coeff_6;
wire [17:0] coeff_7;
wire [37:0] mult_add_result0;
wire [37:0] mult_add_result1;
wire [17:0]shift_data;
//调用 DSP 块 1
mult_add
mult_add_1(.clock0(clock),.aclr3(reset),.ena0(clk_ena),.dataa_0(data_in),
.datab_0(coeff_0),.datab_1(coeff_1),
.datab_2(coeff_2),.datab_3(coeff_3),.resutl(mult_add_result0),
.shitfouta(Shift_data));
//调用 DSP 块 2
Mult_add
Mult_add_2(.clock0(clock),.aclr3(reset),.ena0(clk_ena),.dataa_0(shift_data),
.datab_0(coeff_4), .datab_1(coeff_5),.datab_2(coeff_6),
.datab_3(coeff_7),.result(mult_add_result1));
//读入滤波器系数
coeff_room_0_7 coeff_room_0(.clock(clock),.address(0),.q(coeff_0));
coeff_room_1_6 coeff_room_1(.clock(clock),.address(0),.q(coeff_1));