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XAPP199 (v1.0) June 11, 2001 www.xilinx.com 1

1-800-255-7778

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

Summary This application note is written for logic designers who are new to HDL verification flows, and

who do not have extensive testbench-writing experience.

Testbenches are the primary means of verifying HDL designs. This application note provides

guidelines for laying out and constructing efficient testbenches. It also provides an algorithm to

develop a self-checking testbench for any design.

All design files for this application note are available on the FTP site at:

PC: ftp://ftp.xilinx.com/pub/applications/xapp/xapp199.zip

UNIX: ftp://ftp.xilinx.com/pub/applications/xapp/xapp199.tar.gz

Introduction Due to increases in design size and complexity, digital design verification has become an

increasingly difficult and laborious task. To meet this challenge, verification engineers rely on

several verification tools and methods. For large, multi-million gate designs, engineers typically

use a suite of formal verification tools. However, for smaller designs, design engineers usually

find that HDL simulators with testbenches work best.

Testbenches have become the standard method to verify HLL (High-Level Language) designs.

Typically, testbenches perform the following tasks:

• Instantiate the design under test (DUT)

• Stimulate the DUT by applying test vectors to the model

• Output results to a terminal or waveform window for visual inspection

• Optionally compare actual results to expected results

Typically, testbenches are written in the industry-standard VHDL or Verilog hardware

description languages. Testbenches invoke the functional design, then stimulate it. Complex

testbenches perform additional functions—for example, they contain logic to determine the

proper design stimulus for the design or to compare actual to expected results.

The remaining sections of this note describe the structure of a well-composed testbench, and

provide an example of a self-checking testbench—one that automates the comparison of actual

to expected testbench results.

Figure 1 shows a standard HDL verification flow which follows the steps outlined above.

Since testbenches are written in VHDL or Verilog, testbench verification flows can be ported

across platforms and vendor tools. Also, since VHDL and Verilog are standard non-proprietary

Application Note: Test Benches

XAPP199 (v1.0) June 11, 2001

Writing Efficient Testbenches

Author: Mujtaba Hamid

2 www.xilinx.com XAPP199 (v1.0) June 11, 2001

1-800-255-7778

Writing Efficient Testbenches

languages, verification suites written in VHDL or Verilog can be reused in future designs

without difficulty.

Constructing

Testbenches

Testbenches can be written in VHDL or Verilog. Since testbenches are used for simulation only,

they are not limited by semantic constraints that apply to RTL language subsets used in

synthesis. Instead, all behavioral constructs can be used. Thus, testbenches can be written

more generically, making them easier to maintain.

All testbenches contain the basic sections shown in Table 1. As mentioned, above, testbenches

typically contain additional functionality as well, such as the visual display of results on a

terminal and built-in error detection.

The following examples show some constructs used frequently in testbenches.:

Generating Clock Signals

Designs that use system clocks to sequence logic must generate a clock. Iterative clocks can

easily be implemented in both VHDL and Verilog source code. The following are VHDL and

Verilog examples of clock generation:

VHDL:

-- Declare a clock period constant.

Constant ClockPeriod : TIME := 10 ns;

-- Clock Generation method 1:

Clock <= not Clock after ClockPeriod / 2;

-- Clock Generation method 2:

GENERATE CLOCK: process

begin

Figure 1: HDL Verification Flow Using Testbenches

Testbench Verification Flow

Testbench Instantiates Design

and Provides Stimulus

Design Under Test

(DUT)

Testbench

Displays Values

on Terminal

Verify Result

on Waveform

Testbench

Checks for

Correctness

XAPP199_01_042001

Table 1: Sections Common to Testbenches

VHDL Verilog

Entity and Architecture Declaration Module Declaration

Signal Declaration Signal Declaration

Instantiation of Top-level Design Instantiation of Top-level Design

Provide Stimulus Provide Stimulus

Writing Efficient Testbenches

XAPP199 (v1.0) June 11, 2001 www.xilinx.com 3

1-800-255-7778

wait for (ClockPeriod / 2)

Clock <= ’1’;

wait for (ClockPeriod / 2)

Clock <= ’0’;

end process;

Verilog:

// Declare a clock period constant.

Parameter ClockPeriod = 10;

// Clock Generation method 1:

initial begin

forever Clock = #(ClockPeriod / 2) ~ Clock;

end

// Clock Generation method 2:

initial begin

always #(ClockPeriod / 2) Clock = ~Clock;

end

Providing Stimulus

To obtain testbench verification results, stimulus must be provided to the DUT. Concurrent

stimulus blocks are used in testbenches to provide the necessary stimuli. Two methods are

employed: absolute-time stimulus and relative-time stimulus. In the first method, simulation

values are specified relative to simulation time zero. By comparison, relative-time stimulus

supplies initial values, then waits for an event before retriggering the stimulus. Both methods

can be combined in a testbench, according to the designer’s needs.

Table 2 and Table 3 provide examples of absolute-time and relative-time stimuli, respectively, in

VHDL and Verilog source code.

Table 2: Absolute Time Stimulus Example

VHDL-ABSOLUTE TIME Verilog-ABSOLUTE TIME

MainStimulus: process begin

Reset <= ’1’;

Load <= ’0’;

Count_UpDn <= ’0’;

wait for 100 ns;

Reset <= ’0’;

wait for 20 ns;

Load <= ’1’;

wait for 20 ns;

Count_UpDn <= ’1’;

end process;

initial begin

Reset = 1;

Load = 0;

Count_UpDn = 0;

#100 Reset = 0;

#20 Load = 1;

#20 Count_UpDn = 1;

end

4 www.xilinx.com XAPP199 (v1.0) June 11, 2001

1-800-255-7778

Writing Efficient Testbenches

VHDL process blocks and Verilog initial blocks are executed concurrently along with other

process and initial blocks in the file. However, within each (process or initial) block, events are

scheduled sequentially, in the order written. This means that stimulus sequences begin in each

concurrent block at simulation time zero. Multiple blocks should be used to break up complex

stimulus sequences into more readable and maintainable code.

Displaying Results

Displaying results is facilitated in Verilog by the $display and $monitor keywords. Although

VHDL does not have equivalent display-specific commands, it provides the std_textio package,

which allows file I/O redirection to the display terminal window (for an example of this

technique, see Self-Checking Testbenches, below).

The following is a Verilog example in which values are displayed on the terminal screen:

// pipes the ASCII results to the terminal or text editor

initial begin

$timeformat(-9,1,"ns",12);

$display(" Time Clk Rst Ld SftRg Data Sel");

$monitor("%t %b %b %b %b %b %b", $realtime,

clock, reset, load, shiftreg, data, sel);

end

The $display keyword outputs quoted parenthetical text (“...”) to the terminal window. The

$monitor keyword works differently, since its output is event-driven. In the example, the

$realtime variable (assigned by the user to the current simulation time) is used to trigger the

display of values in the signal list. The signal list starts with the $realtime variable, and is

followed by the names of other signals whose values are to be displayed (clock, reset, load, and

others). The beginning “%” keywords comprise a list of format specifiers, used to control how

each signal value in the signal list is formatted for display. The format list is positional—each

format specifier is sequentially associated with a successive signal name in the signal list. For

example, the %t specifier formats the displayed $realtime value in time format, and the first %b

Table 3: Relative Time Stimulus Example

VHDL-RELATIVE TIME Verilog-RELATIVE TIME

Process (Clock)

Begin

If rising_edge(Clock) then

TB_Count <= TB_Count + 1;

end if;

end process;

SecondStimulus: process begin

if (TB_Count <= 5) then

Reset <= ’1’;

Load <= ’0’;

Count_UpDn <= ’0’;

Else

Reset <= ’0’;

Load <= ‘1’;

Count_UpDn <= ‘1’;

end process;

FinalStimulus: process begin

if (Count = "1100") then

Count_UpDn <= '0';

report "Terminal Count

Reached, now counting down."

end if;

end process;

always @ (posedge clock)

TB_Count <= TB_Count + 1;

initial begin

if (TB_Count <= 5)

begin

Reset = 1;

Load = 0;

Count _UpDn = 0;

end

else

begin

Reset = 0;

Load = 1;

Count_UpDn = 1;

end

initial begin

if (Count == 1100) begin

Count_UpDn <= 0;

$display("Terminal Count

Reached, now counting down.");

end

Writing Efficient Testbenches

XAPP199 (v1.0) June 11, 2001 www.xilinx.com 5

1-800-255-7778

specifier formats the clock value in binary format. Verilog provides additional format-specifiers,

for example, %h is used for hexadecimal, %d for decimal, and %o for octal formats (consult a

Verilog reference for a complete list of keywords and format specifiers).

The formatted display results are shown in Figure 2.

Simple

Testbenches

Simple testbenches instantiate the user design, then provide stimuli to it. Testbench output is

displayed graphically on the simulator's waveform window or as text sent to the user’s terminal

or to a piped text file.

Below is a simple Verilog design representing a shift register:

module shift_reg (clock, reset, load, sel, data, shiftreg);

input clock;

input reset;

input load;

input [1:0] sel;

input [4:0] data;

output [4:0] shiftreg;

reg [4:0] shiftreg;

always @ (posedge clock)

begin

if (reset)

shiftreg = 0;

else if (load)

shiftreg = data;

else

case (sel)

2’b00 : shiftreg = shiftreg;

2’b01 : shiftreg = shiftreg << 1;

2’b10 : shiftreg = shiftreg >> 1;

default : shiftreg = shiftreg;

endcase

end

endmodule

The following simple testbench examples instantiate the shift register design.

Verilog Example:

module testbench; // declare testbench name

reg clock;

reg load;

Figure 2: Simulation Results Echoed to Terminal

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