mxsfb.rar_On Purpose

/* * Copyright (C) 2010 Juergen Beisert, Pengutronix * * This code is based on: * Author: Vitaly Wool <vital@embeddedalley.com> * * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version 2 * of the License, or (at your option) any later version. * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #define DRIVER_NAME "mxsfb" /** * @file * @brief LCDIF driver for i.MX23 and i.MX28 * * The LCDIF support four modes of operation * - MPU interface (to drive smart displays) -> not supported yet * - VSYNC interface (like MPU interface plus Vsync) -> not supported yet * - Dotclock interface (to drive LC displays with RGB data and sync signals) * - DVI (to drive ITU-R BT656) -> not supported yet * * This driver depends on a correct setup of the pins used for this purpose * (platform specific). * * For the developer: Don't forget to set the data bus width to the display * in the imx_fb_videomode structure. You will else end up with ugly colours. * If you fight against jitter you can vary the clock delay. This is a feature * of the i.MX28 and you can vary it between 2 ns ... 8 ns in 2 ns steps. Give * the required value in the imx_fb_videomode structure. */ #include <linux/module.h> #include <linux/kernel.h> #include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/clk.h> #include <linux/dma-mapping.h> #include <linux/io.h> #include <linux/fb.h> #include <linux/regulator/consumer.h> #include <video/of_display_timing.h> #include <video/of_videomode.h> #include <video/videomode.h> #define REG_SET 4 #define REG_CLR 8 #define LCDC_CTRL 0x00 #define LCDC_CTRL1 0x10 #define LCDC_V4_CTRL2 0x20 #define LCDC_V3_TRANSFER_COUNT 0x20 #define LCDC_V4_TRANSFER_COUNT 0x30 #define LCDC_V4_CUR_BUF 0x40 #define LCDC_V4_NEXT_BUF 0x50 #define LCDC_V3_CUR_BUF 0x30 #define LCDC_V3_NEXT_BUF 0x40 #define LCDC_TIMING 0x60 #define LCDC_VDCTRL0 0x70 #define LCDC_VDCTRL1 0x80 #define LCDC_VDCTRL2 0x90 #define LCDC_VDCTRL3 0xa0 #define LCDC_VDCTRL4 0xb0 #define LCDC_DVICTRL0 0xc0 #define LCDC_DVICTRL1 0xd0 #define LCDC_DVICTRL2 0xe0 #define LCDC_DVICTRL3 0xf0 #define LCDC_DVICTRL4 0x100 #define LCDC_V4_DATA 0x180 #define LCDC_V3_DATA 0x1b0 #define LCDC_V4_DEBUG0 0x1d0 #define LCDC_V3_DEBUG0 0x1f0 #define CTRL_SFTRST (1 << 31) #define CTRL_CLKGATE (1 << 30) #define CTRL_BYPASS_COUNT (1 << 19) #define CTRL_VSYNC_MODE (1 << 18) #define CTRL_DOTCLK_MODE (1 << 17) #define CTRL_DATA_SELECT (1 << 16) #define CTRL_SET_BUS_WIDTH(x) (((x) & 0x3) << 10) #define CTRL_GET_BUS_WIDTH(x) (((x) >> 10) & 0x3) #define CTRL_SET_WORD_LENGTH(x) (((x) & 0x3) << 8) #define CTRL_GET_WORD_LENGTH(x) (((x) >> 8) & 0x3) #define CTRL_MASTER (1 << 5) #define CTRL_DF16 (1 << 3) #define CTRL_DF18 (1 << 2) #define CTRL_DF24 (1 << 1) #define CTRL_RUN (1 << 0) #define CTRL1_FIFO_CLEAR (1 << 21) #define CTRL1_SET_BYTE_PACKAGING(x) (((x) & 0xf) << 16) #define CTRL1_GET_BYTE_PACKAGING(x) (((x) >> 16) & 0xf) #define TRANSFER_COUNT_SET_VCOUNT(x) (((x) & 0xffff) << 16) #define TRANSFER_COUNT_GET_VCOUNT(x) (((x) >> 16) & 0xffff) #define TRANSFER_COUNT_SET_HCOUNT(x) ((x) & 0xffff) #define TRANSFER_COUNT_GET_HCOUNT(x) ((x) & 0xffff) #define VDCTRL0_ENABLE_PRESENT (1 << 28) #define VDCTRL0_VSYNC_ACT_HIGH (1 << 27) #define VDCTRL0_HSYNC_ACT_HIGH (1 << 26) #define VDCTRL0_DOTCLK_ACT_FALLING (1 << 25) #define VDCTRL0_ENABLE_ACT_HIGH (1 << 24) #define VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21) #define VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20) #define VDCTRL0_HALF_LINE (1 << 19) #define VDCTRL0_HALF_LINE_MODE (1 << 18) #define VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff) #define VDCTRL0_GET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff) #define VDCTRL2_SET_HSYNC_PERIOD(x) ((x) & 0x3ffff) #define VDCTRL2_GET_HSYNC_PERIOD(x) ((x) & 0x3ffff) #define VDCTRL3_MUX_SYNC_SIGNALS (1 << 29) #define VDCTRL3_VSYNC_ONLY (1 << 28) #define SET_HOR_WAIT_CNT(x) (((x) & 0xfff) << 16) #define GET_HOR_WAIT_CNT(x) (((x) >> 16) & 0xfff) #define SET_VERT_WAIT_CNT(x) ((x) & 0xffff) #define GET_VERT_WAIT_CNT(x) ((x) & 0xffff) #define VDCTRL4_SET_DOTCLK_DLY(x) (((x) & 0x7) << 29) /* v4 only */ #define VDCTRL4_GET_DOTCLK_DLY(x) (((x) >> 29) & 0x7) /* v4 only */ #define VDCTRL4_SYNC_SIGNALS_ON (1 << 18) #define SET_DOTCLK_H_VALID_DATA_CNT(x) ((x) & 0x3ffff) #define DEBUG0_HSYNC (1 < 26) #define DEBUG0_VSYNC (1 < 25) #define MIN_XRES 120 #define MIN_YRES 120 #define RED 0 #define GREEN 1 #define BLUE 2 #define TRANSP 3 #define STMLCDIF_8BIT 1 /** pixel data bus to the display is of 8 bit width */ #define STMLCDIF_16BIT 0 /** pixel data bus to the display is of 16 bit width */ #define STMLCDIF_18BIT 2 /** pixel data bus to the display is of 18 bit width */ #define STMLCDIF_24BIT 3 /** pixel data bus to the display is of 24 bit width */ #define MXSFB_SYNC_DATA_ENABLE_HIGH_ACT (1 << 6) #define MXSFB_SYNC_DOTCLK_FALLING_ACT (1 << 7) /* negtive edge sampling */ enum mxsfb_devtype { MXSFB_V3, MXSFB_V4, }; /* CPU dependent register offsets */ struct mxsfb_devdata { unsigned transfer_count; unsigned cur_buf; unsigned next_buf; unsigned debug0; unsigned hs_wdth_mask; unsigned hs_wdth_shift; unsigned ipversion; }; struct mxsfb_info { struct fb_info fb_info; struct platform_device *pdev; struct clk *clk; struct clk *clk_axi; struct clk *clk_disp_axi; void __iomem *base; /* registers */ unsigned allocated_size; int enabled; unsigned ld_intf_width; unsigned dotclk_delay; const struct mxsfb_devdata *devdata; u32 sync; struct regulator *reg_lcd; }; #define mxsfb_is_v3(host) (host->devdata->ipversion == 3) #define mxsfb_is_v4(host) (host->devdata->ipversion == 4) static const struct mxsfb_devdata mxsfb_devdata[] = { [MXSFB_V3] = { .transfer_count = LCDC_V3_TRANSFER_COUNT, .cur_buf = LCDC_V3_CUR_BUF, .next_buf = LCDC_V3_NEXT_BUF, .debug0 = LCDC_V3_DEBUG0, .hs_wdth_mask = 0xff, .hs_wdth_shift = 24, .ipversion = 3, }, [MXSFB_V4] = { .transfer_count = LCDC_V4_TRANSFER_COUNT, .cur_buf = LCDC_V4_CUR_BUF, .next_buf = LCDC_V4_NEXT_BUF, .debug0 = LCDC_V4_DEBUG0, .hs_wdth_mask = 0x3fff, .hs_wdth_shift = 18, .ipversion = 4, }, }; #define to_imxfb_host(x) (container_of(x, struct mxsfb_info, fb_info)) /* mask and shift depends on architecture */ static inline u32 set_hsync_pulse_width(struct mxsfb_info *host, unsigned val) { return (val & host->devdata->hs_wdth_mask) << host->devdata->hs_wdth_shift; } static inline u32 get_hsync_pulse_width(struct mxsfb_info *host, unsigned val) { return (val >> host->devdata->hs_wdth_shift) & host->devdata->hs_wdth_mask; } static const struct fb_bitfield def_rgb565[] = { [RED] = { .offset = 11, .length = 5, }, [GREEN] = { .offset = 5, .length = 6, }, [BLUE] = { .offset = 0, .length = 5, }, [TRANSP] = { /* no support for transparency */ .length = 0, } }; static const struct fb_bitfield def_rgb888[] = { [RED] = { .offset = 16, .length = 8, }, [GREEN] = { .offset = 8, .length = 8, }, [BLUE] = { .offset = 0, .length = 8, }, [TRANSP] = { /* no support for transparency */ .length = 0, } }; static inline unsigned chan_to_field(unsigned chan, struct fb_bitfield *bf) { chan &= 0xffff; chan >>= 16 - bf->length; return chan << bf->offset; } static int mxsfb_check_var(struct fb_var_screeninfo *var, struct fb_info *fb_info) { struct mxsfb_info *host = to_imxfb_host(fb_info); const struct fb_bitfield *rgb = NULL; if (var->xres < MIN_XRES) var->