Serial ATA:
High Speed Serialized AT Attachment
Revision 1.0
29-August-2001
APT Technologies, Inc.
Dell Computer Corporation
IBM Corporation
Intel Corporation
Maxtor Corporation
Seagate Technology
HIGH SPEED SERIALIZED AT ATTACHMENT Page: 1
SerialATA Workgroup
This 1.0 revision of the Serial ATA / High Speed Serialized AT Attachment specification (“Final
Specification”) is available for product design. Product implementations should ensure
compliance with this specification.
SPECIFICATION DISCLAIMER
THIS SPECIFICATION IS PROVIDED TO YOU “AS IS” WITH NO WARRANTIES
WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE. THE AUTHORS OF THIS
SPECIFICATION DISCLAIM ALL LIABILITY, INCLUDING LIABILITY FOR INFRINGEMENT OF
ANY PROPRIETARY RIGHTS, RELA TING TO USE OR IMPLEMENTATION OF INFORMATION
IN THIS SPECIFICATION. THE AUTHORS DO NOT WARRANT OR REPRESENT THAT SUCH
USE WILL NOT INFRINGE SUCH RIGHTS. THE PROVISION OF THIS SPECIFICATION TO
YOU DOES NOT PROVIDE YOU WITH ANY LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS.
Copyright 2000, 2001, APT Technologies, Inc., Dell Computer Corporation, International
Business Machines Corporation, Intel Corporation, Maxtor Corporation, Seagate Technology
LLC. All rights reserved.
For more information about Serial ATA, refer to the Serial ATA Working Group website at
www.serialata.org.
All product names are trademarks, registered trademarks, or servicemarks of their respective
owners.
Serial ATA Workgroup Technical Editor:
Klaus-Peter Deyring
APT Technologies, Inc.
1347 Pacific Avenue
Suite 205
Santa Cruz, CA 95060 USA
Tel: 831-429-7262
Fax: 831-429-7272
Email: pete@apt-tech.com
HIGH SPEED SERIALIZED AT ATTACHMENT Page: 2
SerialATA Workgroup
Serial ATA Workgroup
Promoters
Klaus-Peter Deyring APT Technologies, Inc.
(831) 429-7262 1347 Pacific Avenue
pete@apt-tech.com Suite 205
Santa Cruz, CA 95060
Ken Jeffries Dell Computer Corp.
(512) 728-9987 One Dell Way
ken_Jeffries@dell.com Round Rock, TX 78682
Frank Chu IBM Corporation
(408) 927-1252 Almaden Research Center
chufr@almaden.ibm.com 650 Harry Road
San Jose, CA 95120
Knut Grimsrud Intel Corp.
(503) 264-8419 M/S JF2-53
knut.s.grimsrud@intel.com 2111 NE 25th Ave
Hillsboro, OR 97124
Marc Noblitt
I/O Planning manager Seagate Technology
(720) 684-1333 phone 389 Disc Drive
(720) 684-1031 fax Longmont, CO
marc_noblitt@seagate.com 80503
Farbod Falakfarsa PTD Architecture Group
(408) 894-4066 500 McCarthy Blvd
Milpitas, CA 95035
Farbod.Falakfarsa@maxtor.com
HIGH SPEED SERIALIZED AT ATTACHMENT Page: 3
SerialATA Workgroup
TABLE OF CONTENTS
1 Scope ...........................................................................................................................11
2 Goals, objectives and migration considerations ...............................................................11
2.1 Goals and objectives ..............................................................................................11
2.2 Migration Considerations ........................................................................................12
3 Normative references ....................................................................................................13
3.1 Approved references ..............................................................................................13
3.2 Other references ....................................................................................................13
4 Definitions, abbreviations, and conventions .....................................................................13
4.1 Definitions and abbreviations ..................................................................................13
4.1.1 ATA (AT Attachment)......................................................................................13
4.1.2 ATAPI (AT Attachment Packet Interface) device ...............................................13
4.1.3 backchannel ...................................................................................................14
4.1.4 bit synchronization ..........................................................................................14
4.1.5 byte ...............................................................................................................14
4.1.6 character........................................................................................................14
4.1.7 character alignment ........................................................................................14
4.1.8 character slipping ...........................................................................................14
4.1.9 code violation .................................................................................................14
4.1.10 comma character ............................................................................................14
4.1.11 comma sequence ...........................................................................................14
4.1.12 command aborted...........................................................................................15
4.1.13 command completion......................................................................................15
4.1.14 command packet ............................................................................................15
4.1.15 Control Block registers ....................................................................................15
4.1.16 control character .............................................................................................15
4.1.17 control variable ...............................................................................................15
4.1.18 CRC ..............................................................................................................15
4.1.19 data character ................................................................................................15
4.1.20 device............................................................................................................15
4.1.21 DMA (direct memory access)...........................................................................15
4.1.22 Dword............................................................................................................16
4.1.23 Dword synchronization ....................................................................................16
4.1.24 encoded character ..........................................................................................16
4.1.25 elasticity buffer ...............................................................................................16
4.1.26 First-party DMA access...................................................................................16
4.1.27 First-party DMA mode .....................................................................................16
4.1.28 FIS ................................................................................................................16
4.1.29 Frame Information Structure............................................................................16
4.1.30 frame .............................................................................................................16
4.1.31 interrupt pending.............................................................................................17
4.1.32 legacy device .................................................................................................17
4.1.33 legacy mode...................................................................................................17
4.1.34 legal character ................................................................................................17
4.1.35 LFSR .............................................................................................................17
4.1.36 PIO (programmed input/output) .......................................................................17
4.1.37 primitive .........................................................................................................17
4.1.38 sector.............................................................................................................17
4.1.39 Shadow Register Block registers .....................................................................17
4.1.40 unrecoverable error.........................................................................................17
4.1.41 word ..............................................................................................................17
4.2 Conventions ..........................................................................................................18
4.2.1 Precedence....................................................................................................18
4.2.2 Keywords .......................................................................................................18
HIGH SPEED SERIALIZED AT ATTACHMENT Page: 4
SerialATA Workgroup
4.2.3 Numbering .....................................................................................................19
4.2.4 Signal conventions ..........................................................................................19
4.2.5 Bit conventions ...............................................................................................19
4.2.6 State diagram conventions ..............................................................................20
4.2.7 Timing conventions .........................................................................................21
4.2.8 Byte, word and Dword Relationships ................................................................22
5 General overview ..........................................................................................................23
5.1 Sub-module operation ............................................................................................25
5.2 Standard ATA Emulation ........................................................................................26
5.2.1 Master-only emulation .....................................................................................26
5.2.2 Master/Slave emulation (optional)....................................................................27
5.2.3 Standard ATA interoperability state diagrams ...................................................29
5.2.4 IDENTIFY DEVICE command..........................................................................33
6 Physical layer................................................................................................................37
6.1 Overview...............................................................................................................37
6.2 List of services .......................................................................................................37
6.3 Cables and connectors specifications ......................................................................38
6.3.1 Overview........................................................................................................38
6.3.2 Objectives ......................................................................................................38
6.3.3 General descriptions .......................................................................................38
6.3.4 Connector configurations and locations ............................................................41
6.3.5 Mating interfaces ............................................................................................44
6.3.6 Serial ATA cable .............................................................................................56
6.3.7 Backplane connector configuration and blind-mating tolerance ..........................56
6.3.8 Connector labeling ..........................................................................................57
6.3.9 Connector and cable assembly requirements and test procedures .....................57
6.4 Low level electronics block diagram ........................................................................68
6.4.1 Diagram .........................................................................................................68
6.4.2 Physical plant overall block diagram description................................................69
6.4.3 Analog front end (AFE) block diagram description .............................................72
6.5 General specifications ............................................................................................73
6.5.1 System...........................................................................................................73
6.6 Module specifications .............................................................................................74
6.6.1 Definitions ......................................................................................................74
6.6.2 Electrical specifications ...................................................................................74
6.6.3 Differential voltage/timing (EYE) diagram ........................................................77
6.6.4 Sampling jitter specifications............................................................................78
6.7 Functional specifications.........................................................................................85
6.7.1 Overview........................................................................................................85
6.7.2 Common-mode biasing ...................................................................................85
6.7.3 Matching ........................................................................................................87
6.7.4 Out of band signaling ......................................................................................87
6.7.5 Idle bus condition............................................................................................96
6.7.6 Elasticity buffer management ...........................................................................96
6.7.7 Test considerations .........................................................................................97
6.8 Interface power states .......................................................................................... 116
6.8.1 Interface power state sequences ................................................................... 117
7 Link layer .................................................................................................................... 127
7.1.1 Overview...................................................................................................... 127
7.2 Encoding method................................................................................................. 127
7.2.1 Notation and conventions .............................................................................. 127
7.2.2 Character code ............................................................................................. 129
7.2.3 Transmission summary ................................................................................. 137
7.2.4 Reception summary ...................................................................................... 139
7.3 Transmission overview......................................................................................... 140
7.4 Primitives ............................................................................................................ 143
