-- i2c.vhd
-- This code implements the control of the i2c bus with a MC68000 type interface. It is
-- modeled from the M-bus component in certain Motorola uC.
-- The I2C control is done in the component i2c_control and the uC interface is implemented
-- in the component uC_interface. This file does not contain any logic descriptions, it simply
-- instantiates the two components and hooks them together.
library IEEE;
use IEEE.std_logic_1164.all;
entity i2c is
generic (I2C_ADDRESS : std_logic_vector(15 downto 0):= "0000000000000000" );
port ( -- I2C bus signals
sda : inout std_logic;
scl : inout std_logic;
-- uC interface signals
addr_bus : in std_logic_vector(23 downto 0);
data_bus : inout std_logic_vector(7 downto 0);
as : in std_logic; -- address strobe, active low
ds : in std_logic; -- data strobe, active low
r_w : in std_logic; -- read/write
dtack : out std_logic;-- data transfer acknowledge
irq : out std_logic;-- interrupt request
mcf : inout std_logic; -- temporary output for testing
-- clock and reset
clk : in std_logic; -- 2MHz to support 100Kbps I2C data transfer rate.
reset : in std_logic
);
end i2c;
library IEEE;
use IEEE.std_logic_1164.all;
architecture behave of i2c is
--***************************** Component Definitions ****************************
-- Define the I2C Control logic
component i2c_control
port(
-- I2C bus signals
sda : inout std_logic;
scl : inout std_logic;
-- interface signals from uP interface
txak : in std_logic; -- value for acknowledge when xmit
msta : in std_logic; -- master/slave select
msta_rst : out std_logic;-- resets MSTA bit if arbitration is lost
