library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity iic_top is
port(
clk: in STD_LOGIC;
rst_n: in STD_LOGIC;
sw1: in STD_LOGIC;
sw2: in STD_LOGIC;
scl: out STD_LOGIC;
sda: inout STD_LOGIC;
sm_cs_n: out STD_LOGIC_VECTOR (1 downto 0);
sm_db: out STD_LOGIC_VECTOR (7 downto 0)
);
end iic_top;
------------------------
architecture iic_top_control of iic_top is
component keycheck is
port(
clk: in STD_LOGIC;
rst_n: in STD_LOGIC;
key: in STD_LOGIC;
sw_en: out STD_LOGIC
);
end component;
----------------------
component iic_com is
port(
clk: in STD_LOGIC;
rst_n: in STD_LOGIC;
sw1_en: in STD_LOGIC;
sw2_en: in STD_LOGIC;
scl: out STD_LOGIC;
sda: inout STD_LOGIC;
dis_data: out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
----------------------
component led_seg7 is
port(
clk: in STD_LOGIC;
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