library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------
entity hkk is
port( clkin:in std_logic;
ctrl:in std_logic_vector(2 downto 0);
dat:out std_logic);
end hkk;
architecture one of hkk is
---------------------------------------------------
component hkk105
port( clki:in std_logic;
clko:out std_logic);
end component;
---------------------------------------------------
signal clkt:std_logic;
signal c7,c15:integer range 0 to 14;
signal m:std_logic;
signal d7,d15,d01,d0,d1:std_logic;
---------------------------------------------------
begin
u1: hkk105 port map(clki=>clkin,clko=>clkt);
---------------------------------------------------
process(clkt)
begin
if rising_edge(clkt) then
if c15=14 then
c15<=0;
else c15<=c15+1;
end if;
end if;
end process;
----------------------------------------------------
process(clkt)
begin
if rising_edge(clkt) then
if c7=6 then
c7<=0;
else c7<=c7+1;
end if;
end if;
end process;
-----------------------------------------------------
process(clkt)
begin
if rising_edge(clkt) then
m<=not m;
end if;
end process;
-----------------------------------------------------
process(c7)
begin
case c7 is
when 3|4|6=>d7<='0';
when others=>d7<='1';
end case;
end process;
------------------------------------------------------
process(c15)
begin
case c15 is
when 0|1|2|3|5|7|8|11=>d15<='1';
when others=>d15<='0';
end case;
end process;
------------------------------------------------------
process(ctrl,d7,d15,d0,d1,d01)
begin
if ctrl="000" then
dat<=d0;
elsif ctrl="001" then
dat<=d1;
elsif ctrl="010" then
dat<=d01;
elsif ctrl="011" then
dat<=d7;
elsif ctrl="100" then
dat<=d15;
end if;
end process;
-----------------------------------------------------
d0<='0';
d1<='1';
d01<=m;
end one;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hkk is
port ( clk,s : in std_logic;
ao, so: out std_logic);
end hkk;
--------------------------------------
architecture tz of hkk is
component hkk2
port( clki:in std_logic;
clko:out std_logic);
end component;
-------------------------------------------
signal q,p,p1,clk2,sou : std_logic;
signal sout,sout1 : std_logic_vector(0 to 1);
begin
u1: hkk2 port map (clki=>clk,clko=>clk2);
-----------------------------------------
process(clk2)
begin
if rising_edge(clk2) then
if s='0' then
sout<="01";
elsif(s='1') then
if q='0' then
sout<="00";
else
sout<="11";
end if;
q<=not q;
end if;
end if;
end process;
------------------------------------
process(clk)
begin
if rising_edge(clk) then
if p='0' then
sou<=sout(0);
else sou<=sout(1);
end if;
p<=not p;
end if;
end process;
so<=sou;
----------------------------------------
process(clk2)
begin
if rising_edge(clk2) then
if sout1="10" then
ao<='0';
elsif(sout1="00" or sout1="11") then
ao<='1';
end if;
end if;
end process;
------------------------------------
process(clk)
begin
if rising_edge(clk) then
if p1='0' then
sout1(0)<=sou;
else sout1(1)<=sou;
end if;
p1<=not p1;
end if;
end process;
end tz;
