library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity reg32b is
port( load:in std_logic;
din:in std_logic_vector(31 downto 0);
dout:out std_logic_vector(31 downto 0));
end reg32b;
architecture behav of reg32b is
begin
process(load,din)
begin
if load'event and load='1' then dout<=din;end if;
end process;
end behav;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder32b is
port(a,b:in std_logic_vector(31 downto 0);
s:out std_logic_vector(31 downto 0));
end adder32b;
architecture behav of adder32b is
begin
s<=a + b;
end behav;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dds is
port( load:in std_logic;
din:in std_logic_vector(31 downto 0);
dout:out std_logic_vector(31 downto 0));
end process;
end behav;