FFT.rar_c5416_fft dsp

/*****************************************************************/ /* Copyright (c) Texas Instruments, Incorporated 2000 */ /*****************************************************************/ /******************************************************************************/ /* MCBSP54.H - MCBSP54 routines header file. */ /* */ /* This module provides the devlib implementation for the MCBSP */ /* on the TMS320C54x DSP. */ /* */ /* MACRO FUNCTIONS: */ /* MCBSP_BYTES_PER_WORD - return # of bytes required to hold # */ /* of bits indicated by wdlen */ /* MCBSP_ENABLE() - starts serial port receive and/or transmit */ /* MCBSP_TX_RESET() - reset transmit side of serial port */ /* MCBSP_RX_RESET() - reset receive side of serial port */ /* MCBSP_DRR1_READ() - read data value from serial port */ /* use instead: MCBSP_SUBREG_READ(... , DRR1_SUBADDR, ... ) */ /* MCBSP_DRR2_READ() - read data value from serial port */ /* use instead: MCBSP_SUBREG_READ(... , DRR2_SUBADDR, ... ) */ /* MCBSP_DRR12_READ() - read data value from serial port */ /* return value as unsigned long */ /* MCBSP_DXR12_WRITE() - write data value from serial port */ /* MCBSP_IO_ENABLE() - place port in general purpose I/O mode */ /* MCBSP_IO_DISABLE() - take port out of general purpose I/O mode */ /* MCBSP_FRAME_SYNC_ENABLE - sets FRST bit in SPCR */ /* MCBSP_FRAME_SYNC_RESET - clrs FRST bit in SPCR */ /* MCBSP_SAMPLE_RATE_ENABLE- sets GRST bit in SPCR */ /* MCBSP_SAMPLE_RATE_RESET - clrs GRST bit in SPCR */ /* MCBSP_RRDY - returns selected ports RRDY */ /* MCBSP_XRDY - returns selected ports XRDY */ /* MCBSP_LOOPBACK_ENABLE - places selected port in loopback */ /* MCBSP_LOOPBACK_DISABLE - takes port out of DLB */ /* */ /* FUNCTIONS: */ /* mcbsp_init - initialize and start serial port operation */ /* */ /* */ /* AUTHOR: */ /* Stefan Haas */ /* */ /* REVISION HISTORY: */ /* */ /* DATE AUTHOR DESCRIPTION */ /* ------- ------------- ------------------------------------------ */ /* 13OCT98 St Haas Original. */ /* */ /******************************************************************************/ /******************************************************************/ /* This header file defines the data structures and macros to */ /* necessary to address the Multi-Channel Serial Port */ /******************************************************************/ #ifndef _MCBSP_H_ #define _MCBSP_H_ #include "regs54xx.h" /* Bits, Bitfields, ... */ #define MCBSP_RX 1 #define MCBSP_TX 2 #define MCBSP_BOTH 3 /* CONFIGURATION REGISTER BIT and BITFIELD values */ /* Serial Port Control Register SPCR1 */ #define DLB_ENABLE 0x01 /* Enable Digital Loopback Mode */ #define DLB_DISABLE 0x00 /* Disable Digital Loopback Mode */ #define RXJUST_RJZF 0x00 /* Receive Right Justify Zero Fill */ #define RXJUST_RJSE 0x01 /* Receive Right Justify Sign Extend */ #define RXJUST_LJZF 0x02 /* Receive Left Justify Zero Fill */ #define CLK_STOP_DISABLED 0x00 /* Normal clocking for non-SPI mode */ #define CLK_START_W/O_DELAY 0x10 /* Clock starts without delay */ #define CLK_START_W_DELAY 0x11 /* Clock starts with delay */ #define DX_ENABLE_OFF 0x00 /* no extra delay for turn-on time */ #define DX_ENABLE_ON 0x01 /* enable extra delay for turn-on time */ #define ABIS_DISABLE 0x00 /* A-bis mode is disabled */ #define ABIS_ENABLE 0x01 /* A-bis mode is enabled */ /* Serial Port Control Registers SPCR1 and SPCR2 */ #define INTM_RDY 0x00 /* R/X INT driven by R/X RDY */ #define INTM_BLOCK 0x01 /* R/X INT driven by new multichannel blk*/ #define INTM_FRAME 0x02 /* R/X INT driven by new frame sync */ #define INTM_SYNCERR 0x03 /* R/X INT generated by R/X SYNCERR */ #define RX_RESET 0x00 /* R or X in reset */ #define RX_ENABLE 0x01 /* R or X enabled */ /* Serial Port Control Register SPCR2 */ #define SP_FREE_OFF 0x00 /* Free running mode is diabled */ #define SP_FREE_ON 0x01 /* Free running mode is enabled */ #define SOFT_DISABLE 0x00 /* SOFT mode is disabled */ #define SOFT_ENABLE 0x01 /* SOFT mode is enabled */ #define FRAME_GEN_RESET 0x00 /* Frame Synchronization logic is reset */ #define FRAME_GEN_ENABLE 0x01 /* Frame sync signal FSG is generated */ #define SRG_RESET 0x00 /* Sample Rate Generator is reset */ #define SRG_ENABLE 0x01 /* Sample Rate Generator is enabled */ /* Pin Control Register PCR */ #define IO_DISABLE 0x00 /* No General Purpose I/O Mode */ #define IO_ENABLE 0x01 /* General Purpose I/0 Mode enabled */ #define CLKR_POL_RISING 0x01 /* R Data Sampled on Rising Edge of CLKR */ #define CLKR_POL_FALLING 0x00 /* R Data Sampled on Falling Edge of CLKR*/ #define CLKX_POL_RISING 0x00 /* X Data Sent on Rising Edge of CLKX */ #define CLKX_POL_FALLING 0x01 /* X Data Sent on Falling Edge of CLKX */ #define FSYNC_POL_HIGH 0x00 /* Frame Sync Pulse Active High */ #define FSYNC_POL_LOW 0x01 /* Frame Sync Pulse Active Low */ #define CLK_MODE_EXT 0x00 /* Clock derived from external source */ #define CLK_MODE_INT 0x01 /* Clock derived from internal source */ #define FSYNC_MODE_EXT 0x00 /* Frame Sync derived from external src */ #define FSYNC_MODE_INT 0x01 /* Frame Sync dervived from internal src */ /* Transmit Receive Control Register XCR/RCR */ #define SINGLE_PHASE 0x00 /* Selects single phase frames */ #define DUAL_PHASE 0x01 /* Selects dual phase frames */ #define MAX_FRAME_LENGTH 0x7f /* maximum number of words per frame */ #define WORD_LENGTH_8 0x00 /* 8 bit word length (requires filling) */ #define WORD_L