TMS320x2833x, 2823x Enhanced Pulse Width
Modulator (ePWM) Module
Reference Guide
Literature Number: SPRUG04
October 2008
Contents
Preface ............................................................................................................................... 9
1 Introduction ............................................................................................................. 13
1.1 Introduction .................................................................................................................. 14
1.2 Submodule Overview ...................................................................................................... 14
1.3 Register Mapping ........................................................................................................... 17
2 ePWM Submodules ................................................................................................... 19
2.1 Overview..................................................................................................................... 20
2.2 Time-Base (TB) Submodule .............................................................................................. 23
2.2.1 Purpose of the Time-Base Submodule ......................................................................... 23
2.2.2 Controlling and Monitoring the Time-base Submodule ....................................................... 24
2.2.3 Calculating PWM Period and Frequency ....................................................................... 25
2.2.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules ......................................... 30
2.2.5 Time-base Counter Modes and Timing Waveforms .......................................................... 30
2.3 Counter-Compare (CC) Submodule ..................................................................................... 32
2.3.1 Purpose of the Counter-Compare Submodule ................................................................ 33
2.3.2 Controlling and Monitoring the Counter-Compare Submodule .............................................. 34
2.3.3 Operational Highlights for the Counter-Compare Submodule ............................................... 35
2.3.4 Count Mode Timing Waveforms ................................................................................ 35
2.4 Action-Qualifier (AQ) Submodule ........................................................................................ 38
2.4.1 Purpose of the Action-Qualifier Submodule ................................................................... 38
2.4.2 Action-Qualifier Submodule Control and Status Register Definitions ...................................... 38
2.4.3 Action-Qualifier Event Priority ................................................................................... 41
2.4.4 Waveforms for Common Configurations ....................................................................... 42
2.5 Dead-Band Generator (DB) Submodule ................................................................................ 51
2.5.1 Purpose of the Dead-Band Submodule ........................................................................ 51
2.5.2 Controlling and Monitoring the Dead-Band Submodule ...................................................... 51
2.5.3 Operational Highlights for the Dead-Band Submodule ....................................................... 52
2.6 PWM-Chopper (PC) Submodule ......................................................................................... 56
2.6.1 Purpose of the PWM-Chopper Submodule .................................................................... 56
2.6.2 Controlling the PWM-Chopper Submodule .................................................................... 56
2.6.3 Operational Highlights for the PWM-Chopper Submodule ................................................... 56
2.6.4 Waveforms ......................................................................................................... 57
2.7 Trip-Zone (TZ) Submodule ................................................................................................ 60
2.7.1 Purpose of the Trip-Zone Submodule .......................................................................... 60
2.7.2 Controlling and Monitoring the Trip-Zone Submodule ........................................................ 61
2.7.3 Operational Highlights for the Trip-Zone Submodule ......................................................... 61
2.7.4 Generating Trip Event Interrupts ................................................................................ 63
2.8 Event-Trigger (ET) Submodule ........................................................................................... 64
2.8.1 Operational Overview of the Event-Trigger Submodule ...................................................... 65
3 Applications to Power Topologies .............................................................................. 69
SPRUG04 – October 2008 Contents 3
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3.1 Overview of Multiple Modules ............................................................................................ 70
3.2 Key Configuration Capabilities............................................................................................ 70
3.3 Controlling Multiple Buck Converters With Independent Frequencies .............................................. 71
3.4 Controlling Multiple Buck Converters With Same Frequencies ...................................................... 75
3.5 Controlling Multiple Half H-Bridge (HHB) Converters ................................................................. 78
3.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM) .................................................... 80
3.7 Practical Applications Using Phase Control Between PWM Modules ............................................... 84
3.8 Controlling a 3-Phase Interleaved DC/DC Converter .................................................................. 85
3.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter ................................................. 89
4 Registers ................................................................................................................. 93
4.1 Time-Base Submodule Registers ........................................................................................ 94
4.2 Counter-Compare Submodule Registers................................................................................ 97
4.3 Action-Qualifier Submodule Registers ................................................................................. 100
4.4 Dead-Band Submodule Registers ...................................................................................... 104
4.5 PWM-Chopper Submodule Control Register .......................................................................... 106
4.6 Trip-Zone Submodule Control and Status Registers ................................................................. 108
4.7 Digital Compare Submodule Registers ................................................................................ 113
4.8 Event-Trigger Submodule Registers ................................................................................... 113
4.9 Proper Interrupt Initialization Procedure ............................................................................... 117
Contents 4 SPRUG04 – October 2008
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List of Figures
1-1 Multiple ePWM Modules ................................................................................................... 15
1-2 Submodules and Signal Connections for an ePWM Module ......................................................... 16
1-3 ePWM Submodules and Critical Internal Signal Interconnects ...................................................... 17
2-1 Time-Base Submodule Block Diagram .................................................................................. 23
2-2 Time-Base Submodule Signals and Registers ......................................................................... 24
2-3 Time-Base Frequency and Period ....................................................................................... 26
2-4 Time-Base Counter Synchronization Scheme 1 ....................................................................... 27
2-5 Time-Base Counter Synchronization Scheme 2 ....................................................................... 28
2-6 Time-Base Counter Synchronization Scheme 3 ....................................................................... 29
2-7 Time-Base Up-Count Mode Waveforms ................................................................................ 30
2-8 Time-Base Down-Count Mode Waveforms ............................................................................. 31
2-9 Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down On Synchronization Event ...... 31
2-10 Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up On Synchronization Event ......... 32
2-11 Counter-Compare Submodule ............................................................................................ 32
2-12 Detailed View of the Counter-Compare Submodule ................................................................... 34
2-13 Counter-Compare Event Waveforms in Up-Count Mode ............................................................. 36
2-14 Counter-Compare Events in Down-Count Mode ....................................................................... 36
2-15 Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down On
Synchronization Event .................................................................................................... 37
2-16 Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up On Synchronization
Event ........................................................................................................................ 37
2-17 Action-Qualifier Submodule ............................................................................................... 38
2-18 Action-Qualifier Submodule Inputs and Outputs ....................................................................... 39
2-19 Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs ............................................ 40
2-20 Up-Down-Count Mode Symmetrical Waveform ........................................................................ 43
2-21 Up, Single Edge Asymmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB—Active High .................................................................................................... 44
2-22 Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and
EPWMxB—Active Low .................................................................................................... 45
2-23 Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA .............. 46
2-24 Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Active Low ................................................................................................... 48
2-25 Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Complementary ............................................................................................. 49
2-26 Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on EPWMxA—Active
Low ........................................................................................................................... 50
2-27 Dead_Band Submodule ................................................................................................... 51
2-28 Configuration Options for the Dead-Band Submodule ................................................................ 52
2-29 Dead-Band Waveforms for Typical Cases (0% < Duty < 100%) ..................................................... 54
2-30 PWM-Chopper Submodule ............................................................................................... 56
2-31 PWM-Chopper Submodule Operational Details ........................................................................ 57
2-32 Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only .................................. 57
2-33 PWM-Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses ......... 58
2-34 PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining
Pulses ........................................................................................................................ 59
2-35 Trip-Zone Submodule ...................................................................................................... 60
2-36 Trip-Zone Submodule Mode Control Logic ............................................................................. 63
2-37 Trip-Zone Submodule Interrupt Logic.................................................................................... 64
2-38 Event-Trigger Submodule ................................................................................................. 64
2-39 Event-Trigger Submodule Inter-Connectivity of ADC Start of Conversion and Interrupt Signals ................ 65
2-40 Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs .......................................... 66
2-41 Event-Trigger Interrupt Generator ........................................................................................ 67
2-42 Event-Trigger SOCA Pulse Generator .................................................................................. 68
SPRUG04 – October 2008 List of Figures 5
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