TMS320x2833x Analog-to-Digital Converter
(ADC) Module
Reference Guide
Literature Number: SPRU812A
September 2007 – Revised October 2007
Contents
Preface ............................................................................................................................... 7
1 Analog-to-Digital Converter (ADC) ................................................................................ 9
1.1 Features ............................................................................................................ 10
1.2 Autoconversion Sequencer Principle of Operation ........................................................... 12
1.2.1 Sequential Sampling Mode ............................................................................. 13
1.2.2 Simultaneous Sampling Mode .......................................................................... 14
1.3 Uninterrupted Autosequenced Mode ........................................................................... 19
1.3.1 Sequencer Start/Stop Mode (Sequencer Start/Stop Operation With Multiple
Time-Sequenced Triggers) ............................................................................. 21
1.3.2 Simultaneous Sampling Mode .......................................................................... 23
1.3.3 Input Trigger Description ............................................................................... 23
1.3.4 Interrupt Operation During Sequenced Conversions ............................................... 24
1.4 ADC Clock Prescaler ............................................................................................. 26
1.4.1 ADC-module Clock and Sample Rate ................................................................. 26
1.5 Low-power Modes ................................................................................................. 26
1.6 Power-up Sequence .............................................................................................. 27
1.7 Sequencer Override Feature .................................................................................... 27
1.8 ADC Calibration ................................................................................................... 28
1.8.1 ADC_Cal Assembly Routine Method .................................................................. 29
1.8.2 Pointer to-Function Method ............................................................................. 29
1.9 Internal/External Reference Voltage Selection ................................................................ 30
1.10 Offset Error Correction............................................................................................ 31
1.11 ADC to DMA Interface ............................................................................................ 32
2 ADC Registers ......................................................................................................... 33
2.1 ADC Control Registers ........................................................................................... 34
2.2 Maximum Conversion Channels Register (ADCMAXCONV) ............................................... 38
2.3 Autosequence Status Register (ADCASEQSR) ............................................................... 40
2.4 ADC Status and Flag Register (ADCST) ....................................................................... 41
2.5 ADC Reference Select Register (ADCREFSEL) .............................................................. 43
2.6 ADC Offset Trim Register (ADCOFFTRIM) .................................................................... 43
2.7 ADC Input Channel Select Sequencing Control Registers .................................................. 44
2.8 ADC Conversion Result Buffer Registers (ADCRESULTn).................................................. 45
SPRU812A – September 2007 – Revised October 2007 Contents 3
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List of Figures
1-1 Block Diagram of the ADC Module ...................................................................................... 11
1-2 Sequential Sampling Mode (SMODE = 0) .............................................................................. 13
1-3 Simultaneous Sampling Mode (SMODE=1) ............................................................................ 14
1-4 Block Diagram of Autosequenced ADC in Cascaded Mode ......................................................... 15
1-5 Block Diagram of Autosequenced ADC With Dual Sequencers .................................................... 16
1-6 Flow Chart for Uninterrupted Autosequenced Mode .................................................................. 21
1-7 Example of ePWM Triggers to Start the Sequencer .................................................................. 22
1-8 Interrupt Operation During Sequenced Conversions ................................................................. 25
1-9 ADC Core Clock and Sample-and-Hold (S/H) Clock .................................................................. 26
1-10 Clock Chain to the ADC ................................................................................................... 26
1-11 External Bias for 2.048-V External Reference .......................................................................... 30
1-12 Flow Chart of Offset Error Correction Process ......................................................................... 31
1-13 Ideal Code Distribution of Sampled 0-V Reference .................................................................... 32
2-1 ADC Control Register 1 (ADCTRL1) (Address Offset 00h) ........................................................... 34
2-2 ADC Control Register 2 (ADCTRL2) (Address Offset 01h) ........................................................... 35
2-3 ADC Control Register 3 (ADCTRL3) (Address Offset 18h) ........................................................... 37
2-4 Maximum Conversion Channels Register (ADCMAXCONV) (Offset Address 02h) .............................. 38
2-5 Autosequence Status Register (ADCASEQSR) (Address Offset 07h) .............................................. 40
2-6 ADC Status and Flag Register (ADCST) (Address Offset 19h) ...................................................... 41
2-7 ADC Reference Select Register (ADCREFSEL) (Address Offset 1Ch) ............................................. 43
2-8 ADC Offset Trim Register (ADCOFFTRIM) (Address Offset 1Dh) .................................................. 43
2-9 ADC Input Channel Select Sequencing Control Registers (ADCCHSELSEQ1) (Address Offset 03h) ......... 44
2-10 ADC Input Channel Select Sequencing Control Registers (ADCCHSELSEQ2) (Address Offset 04h) ......... 44
2-11 ADC Input Channel Select Sequencing Control Registers (ADCCHSELSEQ3) (Address Offset 05h) ......... 44
2-12 ADC Input Channel Select Sequencing Control Registers (ADCCHSELSEQ4) (Address Offset 06h) ......... 44
2-13 ADC Conversion Result Buffer Registers (ADCRESULTn) - (Addresses 0x7108-0x7117) ...................... 45
2-14 ADC Conversion Result Buffer Registers (ADCRESULTn) - (Addresses 0x0B00-0x0B0F) ..................... 45
4 List of Figures SPRU812A – September 2007 – Revised October 2007
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List of Tables
1-1 ADC Registers .............................................................................................................. 11
1-2 Comparison of Single and Cascaded Operating Modes ............................................................. 17
1-3 Values for ADCCHSELSEQn Registers (MAX_CONV1 Set to 6) ................................................... 20
1-4 Values for ADCCHSELSEQn (MAX_CONV1 set to 2) ................................................................ 23
1-5 Values After Second Autoconversion Session ......................................................................... 23
1-6 Input Triggers ............................................................................................................... 23
1-7 Clock Chain to the ADC ................................................................................................... 26
1-8 Power Options .............................................................................................................. 27
2-1 ADC Control Register 1 (ADCTRL1) Field Descriptions .............................................................. 34
2-2 ADC Control Register 2 (ADCTRL2) Field Descriptions .............................................................. 35
2-3 ADC Control Register 3 (ADCTRL3) Field Descriptions ............................................................. 37
2-4 Maximum Conversion Channels Register (ADCMAXCONV) Field Descriptions .................................. 39
2-5 Bit Selections for MAX_CONV1 for Various Number of Conversions .............................................. 39
2-6 Autosequence Status Register (ADCASEQSR) Field Descriptions ................................................. 40
2-7 State of Active Sequencer ................................................................................................ 40
2-8 ADC Status and Flag Register (ADCST) Field Descriptions ......................................................... 41
2-9 ADC Reference Select Register (ADCREFSEL) Field Descriptions ................................................. 43
2-10 ADC Offset Trim Register (ADCOFFTRIM) Field Descriptions ...................................................... 43
2-11 CONVnn Bit Values and the ADC Input Channels Selected ........................................................ 44
SPRU812A – September 2007 – Revised October 2007 List of Tables 5
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