一-----抢答鉴别电路 QDJB 的 VHDL 源程序
--QDJB.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY QDJB IS
PORT(CLR:IN STD_LOGIC;
A,B,C,D:IN STD_LOGIC;
A1,B1,C1,D1:OUT STD_LOGIC;
STATES:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ENTITY QDJB;
ARCHITECTURE ART OF QDJB IS
CONSTANT W1:STD_LOGIC_VECTOR:="0001";
CONSTANT W2:STD_LOGIC_VECTOR:="0010";
CONSTANT W3:STD_LOGIC_VECTOR:="0100";
CONSTANT W4:STD_LOGIC_VECTOR:="1000";
BEGIN
PROCESS(CLR,A,B,C,D)IS
BEGIN
IF CLR='1'THEN STATES<="0000";
ELSIF(A='1'AND B='0'AND C='0'AND D='0')THEN
A1<='1';B1<='0';C1<='0';D1<='0';STATES<=W1;
ELSIF(A='0'AND B='1'AND C='0'AND D='0')THEN
A1<='0';B1<='1';C1<='0';D1<='0';STATES<=W2;
ELSIF(A='0'AND B='0'AND C='1'AND D='0')THEN
A1<='1';B1<='0';C1<='1';D1<='0';STATES<=W3; A1 可能需要改
ELSIF(A='0'AND B='0'AND C='0'AND D='1')THEN
A1<='0';B1<='0';C1<='0';D1<='1';STATES<=W4;
END IF;
END PROCESS;
END ARCHITECTURE ART;
二--------计分器电路 JFQ 的 VHDL 源程序
--JFQ.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY JFQ IS
PORT(RST:IN STD_LOGIC;
ADD:IN STD_LOGIC;
CHOS: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
AA2,AA1,AA0,BB2,BB1,BB0:OUT
STD_LOGIC_VECTOR(3 DOWNTO 0);
CC2,CC1,CC0,DD2,DD1,DD0:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ENTITY JFQ;
ARCHITECTURE ART OF JFQ IS
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