源程序 和 仿真波形图
――AD 控制
LIBRARY
ieee;
--A/D0809
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ad is
port(ST,eoc:in std_logic; --控
制端口
d:in std_logic_vector(7 downto 0);
oe,sta,ale,adda:out std_logic;
q:out std_logic_vector(7 downto 0));
end ad;
architecture a of ad is
type states is(st0,st1,st2,st3,st4,st5,st6); --7 个状态
signal c_state,n_state:states :=st0;
signal regl:std_logic_vector(7 downto 0);
signal lock:std_logic;
begin
adda<='1';
com:process(c_state,eoc)
begin
case c_state is
when st0=>ale<='0';sta<='0';oe<='0';lock<='0';
n_state<=st1;
when st1=>ale<='1';sta<='0';oe<='0';lock<='0';
n_state<=st2;
when st2=>ale<='0';sta<='1';oe<='0';lock<='0';
n_state<=st3;
when st3=>ale<='0';sta<='0';oe<='0';lock<='0';
if(eoc='1') then n_state<=st4;
else n_state<=st3; ――eoc 为‘1’转换结束 进入下一状
态
end if; ――否则 继续转换
when st4=>ale<='0';sta<='0';oe<='1';lock<='0';
n_state<=st5;
when st5=>ale<='0';sta<='0';oe<='0';lock<='1';
n_state<=st6;
when st6=>ale<='0';sta<='0';oe<='0';lock<='1';
