/**
******************************************************************************
* @file GPIO/GPIO_IOToggle/system_stm32f4xx.c
* @author MCD Application Team
* @version V1.4.0
* @date 04-August-2014
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
* This file contains the system clock configuration for STM32F4xx devices.
*
* 1. This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
* and Divider factors, AHB/APBx prescalers and Flash settings),
* depending on the configuration made in the clock xls tool.
* This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f4xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* 2. After each device reset the HSI (16 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to
* configure the system clock before to branch to main program.
*
* 3. If the system clock source selected by user fails to startup, the SystemInit()
* function will do nothing and HSI still used as system clock source. User can
* add some code to deal with this issue inside the SetSysClock() function.
*
* 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
* in "stm32f4xx.h" file. When HSE is used as system clock source, directly or
* through PLL, and you are using different crystal you have to adapt the HSE
* value to your own configuration.
*
* 5. This file configures the system clock as follows:
*=============================================================================
*=============================================================================
* Supported STM32F40xxx/41xxx devices
*-----------------------------------------------------------------------------
* System Clock source | PLL (HSE)
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 168000000
*-----------------------------------------------------------------------------
* HCLK(Hz) | 168000000
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB1 Prescaler | 4
*-----------------------------------------------------------------------------
* APB2 Prescaler | 2
*-----------------------------------------------------------------------------
* HSE Frequency(Hz) | 25000000
*-----------------------------------------------------------------------------
* PLL_M | 25
*-----------------------------------------------------------------------------
* PLL_N | 336
*-----------------------------------------------------------------------------
* PLL_P | 2
*-----------------------------------------------------------------------------
* PLL_Q | 7
*-----------------------------------------------------------------------------
* PLLI2S_N | NA
*-----------------------------------------------------------------------------
* PLLI2S_R | NA
*-----------------------------------------------------------------------------
* I2S input clock | NA
*-----------------------------------------------------------------------------
* VDD(V) | 3.3
*-----------------------------------------------------------------------------
* Main regulator output voltage | Scale1 mode
*-----------------------------------------------------------------------------
* Flash Latency(WS) | 5
*-----------------------------------------------------------------------------
* Prefetch Buffer | ON
*-----------------------------------------------------------------------------
* Instruction cache | ON
*-----------------------------------------------------------------------------
* Data cache | ON
*-----------------------------------------------------------------------------
* Require 48MHz for USB OTG FS, | Disabled
* SDIO and RNG clock |
*-----------------------------------------------------------------------------
*=============================================================================
*=============================================================================
* Supported STM32F42xxx/43xxx devices
*-----------------------------------------------------------------------------
* System Clock source | PLL (HSE)
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 180000000
*-----------------------------------------------------------------------------
* HCLK(Hz) | 180000000
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB1 Prescaler | 4
*-----------------------------------------------------------------------------
* APB2 Prescaler | 2
*-----------------------------------------------------------------------------
* HSE Frequency(Hz) | 25000000
*-----------------------------------------------------------------------------
* PLL_M | 25
*-----------------------------------------------------------------------------
* PLL_N | 360
*-----------------------------------------------------------------------------
* PLL_P | 2
*-----------------------------------------------------------------------------
* PLL_Q | 7
*-----------------------------------------------------------------------------
* PLLI2S_N | NA
*-----------------------------------------------------------------------------
* PLLI2S_R | NA
*-----------------------------------------------------------------------------
* I2S input clock | NA
*-----------------------------------------------------------------------------
* VDD(V) | 3.3
*----
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HC_SR_04.rar_STM32f4 HC-SR04_hc sr04 stm32f4_stm32f4_stm32f4 HC_
共58个文件
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o:11个
crf:10个
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HC_SR_04.rar (58个子文件)
HC_SR_04
KeilC
list
startup_stm32f40_41xxx.lst 93KB
lcd1602test.map 74KB
obj
hcsr04.crf 425KB
hcsr04.d 3KB
stm32f4_delay.d 3KB
lcd1602test.axf 344KB
misc.o 460KB
reprintf.crf 431KB
lcd1602test.build_log.htm 218B
stm32f4xx_rcc.d 3KB
stm32f4xx_gpio.o 464KB
lcd.o 465KB
stm32f4_delay.o 462KB
lcd1602test.lnp 521B
lcd.d 3KB
main.crf 432KB
stm32f4xx_rcc.o 477KB
lcd1602test.sct 479B
stm32f4xx_it.crf 424KB
misc.crf 424KB
stm32f4xx_it.o 459KB
system_stm32f4xx.d 3KB
reprintf.d 3KB
lcd.crf 429KB
reprintf.o 465KB
startup_stm32f40_41xxx.o 8KB
stm32f4xx_gpio.crf 426KB
main.d 3KB
stm32f4xx_rcc.crf 435KB
startup_stm32f40_41xxx.d 124B
stm32f4_delay.crf 424KB
misc.d 3KB
main.o 467KB
lcd1602test.htm 62KB
system_stm32f4xx.crf 426KB
system_stm32f4xx.o 460KB
stm32f4xx_gpio.d 3KB
stm32f4xx_it.d 3KB
hcsr04.o 461KB
hc_sr04.uvopt 11KB
hc_sr04.uvgui_anh vuong.bak 73KB
hc_sr04.uvproj 17KB
hc_sr04_lcd_test.dep 28KB
hc_sr04_hc_sr04.dep 35KB
hc_sr04.uvgui.anh vuong 73KB
LCD_lib
lcd.c 12KB
lcd.h 8KB
reprintf.h 4KB
reprintf.c 3KB
HCSR04_lib
hcsr04.h 2KB
hcsr04.c 2KB
User
main.c 2KB
stm32f4xx_conf.h 4KB
stm32f4xx_it.h 2KB
system_stm32f4xx.c 38KB
stm32f4_delay.c 1KB
stm32f4xx_it.c 4KB
stm32f4_delay.h 1KB
共 58 条
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