代码设计如下:
//16 位原码两位乘法器
module multi_top(product,x,y,clk,reset,start,write_B,write_C);
output[31:0] product;
input[15:0] x,y;
input clk,reset,start,write_B,write_C;
wire
regA_en,regB_en,regC_en,reg_Q_en,mux21_sel,reg_Q_out,modify,regB_en1,regC_en1;
assign regB_en1=write_B|regB_en;
assign regC_en1=write_C|regC_en;
fsm
fsm0(regA_en,regB_en,regC_en,reg_Q_en,mux21_sel,modify,clk,reset,start,reg_Q_ou
t);
bit2_multi
bit2_multi0(product,reg_Q_out,x,y,clk,reset,regA_en,regB_en1,regC_en1,reg_Q_en,
mux21_sel,modify);
endmodule
module
bit2_multi(product,reg_Q_out,x,y,clk,reset,regA_en,regB_en,regC_en,reg_Q_en,mux
21_sel,modify);
output[31:0] product;
output reg_Q_out;
input[15:0] x,y;
input mux21_sel,regA_en,regB_en,regC_en,reg_Q_en,modify;
input clk,reset;
wire[15:0] regA_out,regB_out,regC_out,mux21_out,s,mux_out,product1,product2;
wire regA_en,regB_en,regC_en,c_in,c,reg_Q_out,reg_Q_en,mux21_sel;
reg[1:0] sel;
reg reg_Q_in;
register regA(regA_out,{1'b0,c,s[15:2]},clk,reset,regA_en);
register regB(regB_out,x,clk,reset,regB_en);
register regC(regC_out,mux21_out,clk,reset,regC_en);
bit_add bit_add0(regA_out,mux_out,s,c_in,c);
mux41_16 mux41_16_0(mux_out,16'd0,x,{x[14:0],1'b0},~x,sel);
dff reg_Q(reg_Q_out,reg_Q_in,clk,reset,reg_Q_en);
mux21_16 mux21_16_0(mux21_out,y,{s[1:0],regC_out[15:2]},mux21_sel);
always @(regC_out[1] or regC_out[0] or reg_Q_out)
case({regC_out[1],regC_out[0],reg_Q_out})
3'b000: begin sel=2'b00;reg_Q_in=1'b0; end
3'b001: begin sel=2'b01;reg_Q_in=1'b0; end
3'b010: begin sel=2'b01;reg_Q_in=1'b0; end
3'b011: begin sel=2'b10;reg_Q_in=1'b0; end