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UART2BUS
Open Source
Verificaiton Plan
Opencores.com
Hany Salah
VLSI Verification Engineer
UART2BUS Verificaiton Plan January 2016
Table of Contents
About the Document.............................................................................................................................3
Description.......................................................................................................................................3
References........................................................................................................................................3
Log Details.......................................................................................................................................3
Design Specifications...........................................................................................................................5
Design Port-list................................................................................................................................5
Features............................................................................................................................................6
System Behavioral Description............................................................................................................8
Verification Levels & Required Tools..................................................................................................9
Verification Levels...........................................................................................................................9
Required Tools.................................................................................................................................9
Environment Configurations............................................................................................................9
Methodology & Test Scenario............................................................................................................11
Methodology..................................................................................................................................11
Testing Scenario.............................................................................................................................14
Index of Tables
Log details............................................................................................................................................3
Design Port-List....................................................................................................................................4
Environment Configurations................................................................................................................8
Transaction Attributes.........................................................................................................................10
UART Tests........................................................................................................................................12
Index of Figures
Design Entity........................................................................................................................................4
TestBench Architecture.........................................................................................................................9
2
UART2BUS Verificaiton Plan January 2016
About the Document
Description
This document describes the verification plan used to verify UART2BUS Open-cores project
Released by Moti Litochevski
References
• Bruce Wile, John Goss, Wolfgang Roesner – Comprehensive Functional Verification – The
Complete Industry Cycle – Systems on Silicon (2005).
• System Verilog For Verification – a guide to learning the test-bench language features by
Chris Spear Gregory J Tumbash (2012).
• A Practical Guide to Adopting the Universal Verification Methodology (UVM) by Sharon
Rosenberg, Kathleen Meade – Cadence Design Systems (2010).
Log Details
Table 1: Log details
Version Date Editor Description
1 December 23, 2015 Hany Salah • Document creation
• Add Design Entity
2 December 24, 2015 Hany Salah • Add Design Specifications
• Add System Behavioral Description
• Modify Design Entity
3 December 25, 2015 Hany Salah • Improve System Behavioral Description
• Modify Design Specifications
4 December 29, 2015 Hany Salah • Modify System Behavioral Description.
• Create Test Plan.
5 December 30, 2015 Hany Salah • Improve Test Plan (UART Features).
6 December 31, 2015 Hany Salah • Add Transaction Content.
7 January 01, 2016 Hany Salah • Improve Test Plan (Non UART Features &
Combined Tests & change the tests
serialization).
8 January 11, 2016 Hany Salah • Add Buad Rate Testbench calculations.
• Modify System Behavioral Description
9 January 19, 2016 Hany Salah • Add UART specifications (start, stop bits).
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UART2BUS Verificaiton Plan January 2016
Version Date Editor Description
10 January 24, 2016 Hany Salah • Divide UART fields into commands
• Add Environment Configurations
11 January 29, 2016 Hany Salah • Modify Test Plan
• Modify Environment Configurations
4
UART2BUS Verificaiton Plan January 2016
Design Specifications
Design Port-list
Table 2: Design Port-List
Name Polarity Width Direction Description
clock 1-bit IN Global Core Clock signal
reset high 1-bit IN Global Core Asynchronous Reset
int_address 16-bit OUT Address Bus To Register File
int_wr_data 8-bit OUT Write Data To Register File
int_write high 1-bit OUT Write Control To Register File
int_read high 1-bit OUT Read Control To Register File
int_rd_data 8-bit IN Data Read From Register File
int_req high 1-bit OUT Request Internal bus access
int_gnt high 1-bit IN Grant Internal bus access
ser_in 1-bit IN Serial Data Input
5
figure 1: Design Entity
