PCI Bus Power Management
Interface Specification
Revision 1.1
December 18, 1998
Revision 1.1
2
Revision History
Revision Issue Date Comments
1.0 June 30, 1997 Original Issue.
1.1 December 18, 1998 Integrated the 3.3Vaux ECR.
DISCLAIMER
This PCI Bus Power Management Interface Specification is provided "as is" with no warranties
whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular
purpose, or any warranty otherwise arising out of any proposal, specification, or sample. The PCI
SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this
specification. No license, express or implied, by estoppel or otherwise, to any intellectual property
rights is granted herein.
Intel and Pentium are registered trademarks of Intel Corporation.
OnNow and Windows NT are trademarks and Microsoft, Windows, and Win32 are registered trademarks of Microsoft
Corporation.
All other product names are trademarks, registered trademarks, or servicemarks of their respective owners.
Copyright © 1997, 1998 PCI Special Interest Group
All rights reserved.
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Contents
Chapter 1 Introduction
1.1 Goals of This Specification.................................................................................................... 10
1.2 Target Audience .................................................................................................................... 10
1.3 Overview/Scope .................................................................................................................... 11
1.4 Glossary of Terms ................................................................................................................. 12
1.5 Related Documents................................................................................................................ 16
1.6 Conventions Used in This Document.................................................................................... 16
Chapter 2 PCI Power Management Overview
2.1 PCI Power Management States ............................................................................................. 17
2.1.1 PCI Function Power States.................................................................................... 17
2.1.2 Bus Power States................................................................................................... 17
2.1.3 Device-Class Specifications.................................................................................. 18
2.1.4 Bus Support for PCI Function Power Management.............................................. 19
Chapter 3 PCI Power Management Interface
3.1 Capabilities List Data Structure ............................................................................................ 22
3.1.1 Capabilities List Cap_Ptr Location ....................................................................... 23
3.2 Power Management Register Block Definition..................................................................... 24
3.2.1 Capability Identifier - Cap_ID (Offset = 0) .......................................................... 24
3.2.2 Next Item Pointer - Next_Item_Ptr (Offset = 1)................................................... 25
3.2.3 PMC - Power Management Capabilities (Offset = 2)........................................... 25
3.2.4 PMCSR - Power Management Control/Status (Offset = 4).................................. 27
3.2.5 PMCSR_BSE - PMCSR PCI to PCI Bridge Support Extensions (Offset = 6)..... 30
3.2.6 Data (Offset = 7).................................................................................................... 30
Chapter 4 PCI Power States
4.1 PCI B0 State - Fully On......................................................................................................... 34
4.2 PCI B1 State ..........................................................................................................................34
4.3 PCI B2 State ..........................................................................................................................35
4.4 PCI B3 State - Off.................................................................................................................. 35
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4.5 PCI Bus Power State Transitions .......................................................................................... 36
4.6 PCI Clocking Considerations ................................................................................................ 36
4.6.1 Special Considerations for 66-MHz PCI Designs................................................. 37
4.7 Control/Status of PCI Bus Power Management States ......................................................... 38
4.7.1 Control of Secondary Bus Power Source and Clock............................................. 38
Chapter 5 PCI Function Power Management States
5.1 PCI Function D0 State........................................................................................................... 41
5.2 PCI Function D1 State........................................................................................................... 42
5.3 PCI Function D2 State........................................................................................................... 42
5.4 PCI Function D3 State........................................................................................................... 42
5.4.1 Software Accessible D3 (D3
hot
) ............................................................................. 43
5.4.2 Power Off (D3
cold
) .................................................................................................. 43
5.4.3 3.3Vaux / D3
cold
Card Power Consumption Requirements .................................... 43
5.5 PCI Function Power State Transitions .................................................................................. 44
5.6 PCI Function Power Management Policies........................................................................... 45
5.6.1 State Transition Recovery Time Requirements .................................................... 50
Chapter 6 PCI Bridges and Power Management
6.1 Host Bridge or Other Motherboard Enumerated Bridge....................................................... 53
6.2 PCI to PCI Bridges ................................................................................................................ 54
6.3 PCI to CardBus Bridge.......................................................................................................... 54
Chapter 7 Power Management Events
7.1 Power Management Event (PME#) Signal Routing.............................................................. 58
7.2 Auxiliary Power..................................................................................................................... 59
7.2.1 3.3Vaux DC Characteristics:................................................................................. 59
7.2.2 3.3Vaux Minimum Required Current Capacity .................................................... 60
7.3 3.3Vaux System Design Requirements................................................................................. 60
7.3.1 Power Delivery Requirements............................................................................... 60
7.3.2 PCI Bus RST# Signaling Requirements............................................................... 61
7.3.3 Voltage Sequencing............................................................................................... 62
7.4 3.3Vaux Add-in Card Design Requirements......................................................................... 62
7.4.1 3.3Vaux Power Consumption Requirements ........................................................ 62
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7.4.2 Physical Connection to the 3.3Vaux pin ............................................................... 62
7.4.3 Isolation of 3.3Vaux from Main 3.3V................................................................... 62
7.4.4 3.3Vaux Presence Detection.................................................................................. 63
Chapter 8 Software Support for PCI Power Management
8.1 Identifying PCI Function Capabilities................................................................................... 65
8.2 Placing PCI Functions in a Low Power State........................................................................ 66
8.2.1 Buses...................................................................................................................... 66
8.2.2 D3 State ................................................................................................................. 66
8.3 Restoring PCI Functions From a Low Power State .............................................................. 66
8.3.1 D0 “Uninitialized” and the DSI Bit....................................................................... 66
8.3.2 D1 and D2 States................................................................................................... 67
8.3.3 D3 State ................................................................................................................. 67
8.4 Wake Events.......................................................................................................................... 68
8.4.1 Wake Event Support.............................................................................................. 68
8.4.2 The D0 “Initialized” State From a Wake Event.................................................... 68
8.5 Get Capabilities..................................................................................................................... 69
8.6 Set Power State...................................................................................................................... 69
8.7 Get Power Status ................................................................................................................... 69
8.8 System BIOS Initialization.................................................................................................... 69
Chapter 9 Other Considerations
