caideng.rar_caideng_vhdl

LIBRARY IEEE; --使用的库和程序包 USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; entity VH8 is --VH8的外部说明 port(clk_in,control:in std_logic; output:out std_logic_vector(8 downto 0)); end VH8 ; architecture lsy of VH8 is signal cnt:integer range 0 to 24999999; signal clk_out,CON:std_logic; signal P:std_logic_vector(8 downto 0); begin process(clk_in) begin if (clk_in'event and clk_in='1') then --分频器 if cnt=24999999 then cnt<=0; clk_out<= not clk_out; else cnt<=cnt+1; end if; end if; end process; process(clk_out) BEGIN IF (CONTROL'EVENT AND CONTROL='1') THEN CON<=NOT CON; ELSE CON <=CON; END IF; if (clk_out'event and clk_out='1') then --单点移动模式 if CON='0' then P<="000000000"; case P is when"000000000"=>P<="010000000"; when"010000000"=>P<="001000000"; when"001000000"=>P<="000100000"; when"000100000"=>P<="000010000"; when"000010000"=>P<="000001000"; when"000001000"=>P<="000000100"; when"000000100"=>P<="000000010"; when"000000010"=>P<="000000001"; when"000000001"=>P<="100000010"; when"100000010"=>P<="100000100"; when"100000100"=>P<="100001000"; when"100001000"=>P<="100010000"; when"100010000"=>P<="100100000"; when"100100000"=>P<="101000000"; when"101000000"=>P<="110000000"; when"110000000"=>P<="000000000"; when others=>P<="000000000"; end case; else P<="000000000"; --幕布式 case P is when"000000000"=>P<="000011000"; when"000011000"=>P<="000111100"; when"000111100"=>P<="001111110"; when"001111110"=>P<="011111111"; when"011111111"=>P<="101111110"; when"101111110"=>P<="100111100"; when"100111100"=>P<="100011000"; when"100011000"=>P<="000000000"; when others=>P<="000000000"; end case; end if; end if; end process; output<=P; END lsy;