library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity caideng is
port(ds,reset,clk,huan:in std_logic;
dout:buffer std_logic_vector(7 downto 0));
end caideng;
architecture a of caideng is
signal temp:std_logic_vector(1 downto 0);
begin
temp<=huan&ds;
process(clk,reset)
begin
if(clk'event and clk='1')then
if(reset='1')then
if temp="00" then dout<="10000000";
elsif temp="01" then dout<="00000001";
elsif temp="10" then dout<="00011000";
elsif temp="11" then dout<="10000001";
end if;
elsif temp="10" then
dout(3 downto 0)<=dout(0)&dout(3 downto 1);
dout(7 downto 4)<=dout(6 downto 4)&dout(7);
elsif temp="11" then
dout(7 downto 4)<=dout(4)&dout(7 downto 5);
dout(3 downto 0)<=dout(2 downto 0)&dout(3);
elsif temp="00" then
dout<=dout(0)&dout(7 downto 1);
elsif temp="01" then
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