8位串行输入,串行输出移位寄存器
-- Quartus VHDL Template
-- Clearable loadable enablable counter
LIBRARY ieee;
USE ieee.std_logic_1164.all;
xENTITY start IS
PORT
(
a,clk:in std_logic;
b: out std_logic
);
END start;
ARCHITECTURE a OF start IS
component mydff
port (
d,clk:in std_logic;
q:out std_logic
);
end component;
SIGNAL z :std_logic_vector(0 to 8);
begin
Z(0)<=a;
gl:for i in 0 to 7 generate
dffx: mydff port map (z(i),clk,z(i+1));
end generate;
b<=z(8);
end a;
library ieee;
use ieee.std_logic_1164.all;
entity mydff is
port (
clk,d:in std_logic;
q: out std_logic
);
end mydff;
architecture a of mydff is
begin
process(clk)
begin
if(clk'event and clk='1') then
q<=d;
end if;
end process;
end a;
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