################################################################################
# Vivado (TM) v2019.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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频率响应屏蔽(FRM)滤波器设计源代码及仿真
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采用vivado编程软件,带有tb文件,可进行功能仿真。
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频率响应屏蔽(FRM)滤波器设计源代码及仿真 (693个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
xsim.ini.bak 26KB
elaborate.bat 1KB
compile.bat 996B
simulate.bat 924B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
xsim_2.c 175KB
xsim_1.c 57KB
tb_hb_fir_no_int.c 8KB
tb_fir_ma.c 8KB
tb_fir_mc.c 8KB
fir_yx_49p152_56p5248.coe 826B
fir_yx_49p152_56p5248.coe 826B
fir_yx_49p152_56p5248.coe 826B
fir_yx_49p152_56p5248.coe 826B
fir_yx_49p152_56p5248.coe 826B
fir_yx_49p152_56p5248.coe 826B
fir_yx_49p152_56p5248.coe 826B
fir_yx_49p152_56p5248.coe 826B
fir_yx_49p152_56p5248.coe 826B
fir_yx_49p152_56p5248.coe 826B
fir_mc_33p177_50p3808.coe 490B
fir_mc_33p177_50p3808.coe 490B
fir_mc_33p177_50p3808.coe 490B
fir_mc_33p177_50p3808.coe 490B
fir_mc_33p177_50p3808.coe 490B
fir_mc_33p177_50p3808.coe 490B
fir_mc_33p177_50p3808.coe 490B
fir_mc_33p177_50p3808.coe 490B
fir_yx_26p05_45p71.coe 490B
fir_mc_33p177_50p3808.coe 490B
fir_yx_26p05_45p71.coe 490B
fir_mc_33p177_50p3808.coe 490B
hb_no_int.coe 466B
hb_no_int.coe 466B
fir_ma_49p152_72p499.coe 418B
fir_ma_49p152_72p499.coe 418B
fir_ma_49p152_72p499.coe 418B
fir_ma_49p152_72p499.coe 418B
fir_ma_49p152_72p499.coe 418B
fir_ma_49p152_72p499.coe 418B
fir_ma_49p152_72p499.coe 418B
fir_ma_49p152_72p499.coe 418B
fir_ma_49p152_72p499.coe 418B
fir_ma_49p152_72p499.coe 418B
xsim.dbg 16KB
hb_fir_no_int.dcp 1.55MB
hb_fir_no_int.dcp 1.55MB
hb_fir_no_int.dcp 1.55MB
hb_fir_no_int.dcp 1.39MB
hb_fir_no_int.dcp 704KB
fir_mc.dcp 639KB
fir_mc.dcp 639KB
fir_mc.dcp 638KB
fir_ma.dcp 477KB
fir_ma.dcp 477KB
fir_ma.dcp 476KB
fir_ma.dcp 475KB
hb_fir_no_int.dcp 367KB
shift_ram.dcp 105KB
shift_ram.dcp 105KB
shift_ram.dcp 105KB
shift_ram_delay.dcp 54KB
shift_ram.dcp 36KB
shift_ram_delay.dcp 36KB
top.dcp 29KB
shift_ram.dcp 27KB
compile.do 1KB
compile.do 1KB
compile.do 1KB
compile.do 1KB
compile.do 961B
compile.do 949B
compile.do 939B
compile.do 927B
compile.do 880B
compile.do 866B
compile.do 866B
compile.do 860B
compile.do 846B
compile.do 846B
compile.do 779B
compile.do 765B
compile.do 765B
compile.do 761B
compile.do 747B
compile.do 747B
simulate.do 353B
simulate.do 353B
simulate.do 352B
simulate.do 340B
simulate.do 335B
simulate.do 335B
simulate.do 327B
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