Digital-electronics-1

Digital-electronics-1 实验室 源代码 architecture dataflow of gates is begin f_o <= (( not b_i) and a_i) or (( not c_i) and ( not b_i)); fnand_o <= -- fand_o <= a_i and b_i; -- fxor_o <= a_i xor b_i; end architecture dataflow ; | ** c ** | ** b ** |** a ** | ** f(c,b,a) ** | | : - : | : - : | : - : | : - : | | 0 | 0 | 0 | | | 0 | 0 | 1 | | | 0 | 1 | 0 | | | 0 | 1 | 1 | | | 1 | 0 |