Section number Title Page
Functional Safety
6.1 Introduction...................................................................................................................................................................171
Chapter 7
Chip Configuration
7.1 Introduction...................................................................................................................................................................173
7.2 Core modules................................................................................................................................................................ 173
7.2.1 Core reset settings........................................................................................................................................ 173
7.2.2 Special Purpose Register summary..............................................................................................................175
7.2.3 Core reservation instructions....................................................................................................................... 178
7.3 Platform Configuration Module (PCM)........................................................................................................................178
7.3.1 Bus Bridge Configuration Register 1 (PCM_IAHB_BE1)..........................................................................179
7.3.2 Bus Bridge Configuration Register 2 (PCM_IAHB_BE2)..........................................................................180
7.3.3 Bus Bridge Configuration Register 3 (PCM_IAHB_BE3)..........................................................................181
7.4 System modules............................................................................................................................................................ 182
7.4.1 System Integration Unit Lite2 (SIUL2) configuration.................................................................................182
7.4.2 Crossbar Switch Integrity Checker (XBIC) configuration.......................................................................... 183
7.4.3 Crossbar Switch (XBAR) configuration .....................................................................................................185
7.4.4 System Memory Protection Unit (SMPU) configuration............................................................................ 188
7.4.5 Peripheral Bridge configuration...................................................................................................................189
7.4.6 Interrupt Controller (INTC) configuration...................................................................................................192
7.4.7 DMA Controller configuration.................................................................................................................... 203
7.4.8 DMAMUX configuration ........................................................................................................................... 204
7.4.9 Error Injection Module (EIM) configuration...............................................................................................206
7.5 Clocking .......................................................................................................................................................................207
7.6 Memories and memory interfaces.................................................................................................................................207
7.6.1 RAM controller (PRAMC) configuration....................................................................................................207
7.6.2 Flash Memory Controller (PFLASH) configuration ...................................................................................208
7.6.3 Embedded Flash Memory (c55fmc) configuration......................................................................................208
7.6.4 Decorated Storage Memory Controller (DSMC) configuration.................................................................. 218
MPC5744P Reference Manual, Rev. 6, 06/2016
NXP Semiconductors 5