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NXP Semiconductors
Document Number: MPC5744PRM
Rev. 6.1, 10/2017
This is the MPC5744P Reference Manual set, consisting of the following files:
• MPC5744P Reference Manual Addendum, Rev. 2
• MPC5744P Reference Manual, Rev. 6
MPC5744P Reference Manual
MPC5744P Reference Manual
Addendum
Updates to the MPC5744P Reference Manual, Revision 6
Document Number: MPC5744PRMAD
Rev. 2, 10/2017
MPC5744P Reference Manual Addendum, Rev. 2, 10/2017
2 NXP Semiconductors
Contents
Section number Title Page
Chapter 1
Addendum for Rev. 6 of MPC5744PRM
1.1 Introduction.....................................................................................................................................................................11
Chapter 2
RM Addendum
2.1 Introduction.....................................................................................................................................................................25
2.1.1 Block Diagram................................................................................................................................................. 25
2.2 Signal Description...........................................................................................................................................................26
2.2.1 MPC5744P features differing by package....................................................................................................... 26
2.2.2 GPIO safe state configuration..........................................................................................................................27
2.2.3 System pins/balls..............................................................................................................................................28
2.2.4 LVDS pins/balls...............................................................................................................................................29
2.2.5 Pin muxing....................................................................................................................................................... 29
2.3 Memory Map.................................................................................................................................................................. 77
2.3.1 Memory Map....................................................................................................................................................77
2.4 Chip Configuration......................................................................................................................................................... 88
2.4.1 Crossbar Switch Integrity Checker (XBIC) configuration.............................................................................. 88
2.4.2 Crossbar Switch (XBAR) configuration .........................................................................................................90
2.4.3 High priority requests.......................................................................................................................................91
2.4.4 DMA Controller configuration........................................................................................................................ 92
2.4.5 PACR/OPACR registers.................................................................................................................................. 92
2.4.6 Flash Memory Controller (PFLASH) configuration........................................................................................95
2.4.7 eTimer auxiliary input connection .................................................................................................................. 95
2.4.8 CTU inter-module connections........................................................................................................................96
2.4.9 Serial Peripheral Interface (SPI) configuration ...............................................................................................96
2.4.10 LINFlexD configuration ................................................................................................................................. 97
2.4.11 SSCM_MEMCONFIG reset value.................................................................................................................. 97
2.4.12 Fault inputs.......................................................................................................................................................98
MPC5744P Reference Manual Addendum, Rev. 2, 10/2017
NXP Semiconductors 3
Section number Title Page
2.4.13 FCCU chip-specific register reset values.........................................................................................................103
2.4.14 FCCU_CFG register event bit values by source (N and C).............................................................................103
2.5 Reset................................................................................................................................................................................104
2.5.1 Module Status During Reset Process...............................................................................................................104
2.6 Device Configuration Format (DCF) Records................................................................................................................106
2.6.1 DCF clients available in the device..................................................................................................................106
2.6.2 FCCU record....................................................................................................................................................108
2.7 Debug..............................................................................................................................................................................109
2.7.1 Device identification register reset values....................................................................................................... 110
2.7.2 DID register reset and parameter values..........................................................................................................110
2.7.3 Trace messages for transactions with error responses..................................................................................... 110
2.7.4 Features............................................................................................................................................................ 110
2.7.5 Nexus Aurora clocking.................................................................................................................................... 111
2.8 Power Management........................................................................................................................................................ 111
2.8.1 Supply Concept................................................................................................................................................111
2.9 Clocking..........................................................................................................................................................................112
2.9.1 System clock frequency limitations................................................................................................................. 113
2.9.2 System clock frequency limitations................................................................................................................. 113
2.9.3 JTAG Frequencies............................................................................................................................................114
2.9.4 Peripheral clocks..............................................................................................................................................115
2.9.5 LFAST clocking...............................................................................................................................................117
2.10 e200z4d Core Complex Overview..................................................................................................................................117
2.10.1 Overview of e200z4251n3 and e200z424 cores.............................................................................................. 117
2.11 Core Detailed Description...............................................................................................................................................118
2.11.1 DMEM Control Register 0 (DMEMCTL0).....................................................................................................118
2.12 System Integration Unit Lite2.........................................................................................................................................123
2.12.1 SIUL2 MCU ID Register................................................................................................................................. 123
2.13 Enhanced Direct Memory Access...................................................................................................................................124
2.13.1 TCD Control and Status Register.....................................................................................................................124
MPC5744P Reference Manual Addendum, Rev. 2, 10/2017
4 NXP Semiconductors
