【免费】模数转换DAC0832的应用-输出0~5V的锯齿波或三角波资源-CSDN文库

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013 模数转换 DAC0832的应用--输出0~5V的锯齿波或三角波.zip （25个子文件）

013 模数转换 DAC0832的应用--输出0~5V的锯齿波或三角波

~$DA转换器－DAC0832.doc 162B

DAC0832.PDF 532KB

电路图.PWI 316B

keil

chengxu.lnp 62B

chengxu.uvproj 13KB

STARTUP.LST 14KB

chengxu.M51 8KB

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chengxu_Opt.Bak 1KB

chengxu.OBJ 4KB

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chengxu 4KB

chengxu.c 2KB

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chengxu_Uv2.Bak 2KB

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chengxu.uvopt 6KB

chengxu.LST 4KB

chengxu.uvgui.Administrator 70KB

Last Loaded 电路图.DBK 77KB

DAC0832.doc 1008KB

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8位DA转换器－DAC0832.doc 1.88MB

DAC0830/DAC0832

8-Bit µP Compatible, Double-Buffered D to A Converters

General Description

The DAC0830 is an advanced CMOS/Si-Cr 8-bit multiplying

DAC designed to interface directly with the 8080, 8048,

8085, Z80

, and other popular microprocessors. A deposited

silicon-chromium R-2R resistor ladder network divides the

reference current and provides the circuit with excellent tem-

perature tracking characteristics (0.05

of Full Scale Range

maximum linearity error over temperature). The circuit uses

CMOS current switches and control logic to achieve low

power consumption and low output leakage current errors.

Special circuitry provides TTL logic input voltage level com-

patibility.

Double buffering allows these DACs to output a voltage cor-

responding to one digital word while holding the next digital

word. This permits the simultaneous updating of any number

of DACs.

The DAC0830 series are the 8-bit members of a family of

microprocessor-compatible DACs (MICRO-DAC

™

Features

n Double-buffered, single-buffered or flow-through digital

data inputs

n Easy interchange and pin-compatible with 12-bit

DAC1230 series

n Direct interface to all popular microprocessors

n Linearity specified with zero and full scale adjust

only — NOT BEST STRAIGHT LINE FIT.

n Works with

10V reference-full 4-quadrant multiplication

n Can be used in the voltage switching mode

n Logic inputs which meet TTL voltage level specs (1.4V

logic threshold)

n Operates “STAND ALONE” (without µP) if desired

n Available in 20-pin small-outline or molded chip carrier

package

Key Specifications

n Current settling time: 1 µs

n Resolution: 8 bits

n Linearity: 8, 9, or 10 bits (guaranteed over temp.)

n Gain Tempco: 0.0002

FS/˚C

n Low power dissipation: 20 mW

n Single power supply: 5 to 15 V

Typical Application

BI-FET

™

and MICRO-DAC

™

are trademarks of National Semiconductor Corporation.

Z80

is a registered trademark of Zilog Corporation.

DS005608-1

May 1999

DAC0830/DAC0832 8-Bit µP Compatible, Double-Buffered D to A Converters

Connection Diagrams (Top Views)

Dual-In-Line and

Small-Outline Packages

DS005608-21

Molded Chip Carrier Package

DS005608-22

www.national.com 2

Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage (V

)17V

Voltage at Any Digital Input V

to GND

Voltage at V

REF

Input

25V

Storage Temperature Range −65˚C to +150˚C

Package Dissipation

at T

25˚C (Note 3) 500 mW

DC Voltage Applied to

OUT1

or I

OUT2

(Note 4) −100 mV to V

ESD Susceptability (Note 4) 800V

Lead Temperature (Soldering, 10 sec.)

Dual-In-Line Package (plastic) 260˚C

Dual-In-Line Package (ceramic) 300˚C

Surface Mount Package

Vapor Phase (60 sec.) 215˚C

Infrared (15 sec.) 220˚C

Operating Conditions

Temperature Range T

MIN

≤T

MAX

Part numbers with “LCN” suffix 0˚C to +70˚C

Part numbers with “LCWM” suffix 0˚C to +70˚C

Part numbers with “LCV” suffix 0˚C to +70˚C

Part numbers with “LCJ” suffix −40˚C to +85˚C

Part numbers with “LJ” suffix −55˚C to +125˚C

Voltage at Any Digital Input V

to GND

Electrical Characteristics

REF

10.000 V

unless otherwise noted. Boldface limits apply over temperature, T

MIN

≤T

MAX

. For all other limits

25˚C.

Parameter Conditions

See

Note

4.75 V

15.75 V

12 V

to 15 V

Limit

Units

Typ

(Note 12)

Tested

Limit

(Note 5)

Design

Limit

(Note 6)

CONVERTER CHARACTERISTICS

Resolution 88 8 bits

Linearity Error Max Zero and full scale adjusted 4, 8

−10V≤V

REF

≤+10V

DAC0830LJ & LCJ 0.05 0.05

FSR

DAC0832LJ & LCJ 0.2 0.2

FSR

DAC0830LCN, LCWM &

LCV

0.05 0.05

FSR

DAC0831LCN 0.1 0.1

FSR

DAC0832LCN, LCWM &

LCV

0.2 0.2

FSR

Differential Nonlinearity Zero and full scale adjusted 4, 8

Max −10V≤V

REF

≤+10V

DAC0830LJ & LCJ 0.1 0.1

FSR

DAC0832LJ & LCJ 0.4 0.4

FSR

DAC0830LCN, LCWM &

LCV

0.1 0.1

FSR

DAC0831LCN 0.2 0.2

FSR

DAC0832LCN, LCWM &

LCV

0.4 0.4

FSR

Monotonicity −10V≤V

REF

LJ & LCJ 4 88bits

≤+10V LCN, LCWM & LCV 8 8 bits

Gain Error Max Using Internal R

0.2

−10V≤V

REF

≤+10V

Gain Error Tempco Max Using internal R

0.0002 0.0006

FS/˚C

Power Supply Rejection All digital inputs latched high

14.5V to 15.5V 0.0002 0.0025

11.5V to 12.5V 0.0006 FSR/V

4.5V to 5.5V 0.013 0.015

Reference Max 15 20 20 kΩ

Input Min 15 10 10 kΩ

Output Feedthrough Error V

REF

20 Vp-p, f

100 kHz

All data inputs latched low

3 mVp-p

www.national.com3

Electrical Characteristics (Continued)

REF

10.000 V

unless otherwise noted. Boldface limits apply over temperature, T

MIN

≤T

MAX

. For all other limits

25˚C.

Parameter Conditions

See

Note

4.75 V

15.75 V

12 V

to 15 V

Limit

Units

Typ

(Note 12)

Tested

Limit

(Note 5)

Design

Limit

(Note 6)

CONVERTER CHARACTERISTICS

Output Leakage

Current Max

OUT1

All data inputs LJ & LCJ 10 100 100 nA

latched low LCN, LCWM & LCV 50 100

OUT2

All data inputs LJ & LCJ 100 100 nA

latched high LCN, LCWM & LCV 50 100

Output I

OUT1

All data inputs 45 pF

Capacitance I

OUT2

latched low 115

OUT1

All data inputs 130 pF

OUT2

latched high 30

DIGITAL AND DC CHARACTERISTICS

Digital Input Max Logic Low LJ: 4.75V 0.6

Voltages LJ: 15.75V 0.8

LCJ: 4.75V 0.7 V

LCJ: 15.75V 0.8

LCN, LCWM, LCV 0.95 0.8

Min Logic High LJ & LCJ 2.0 2.0 V

LCN, LCWM, LCV 1.9 2.0

Digital Input Max Digital inputs

0.8V

Currents LJ & LCJ −50 −200 −200 µA

LCN, LCWM, LCV −160 −200 µA

Digital inputs

2.0V

LJ & LCJ 0.1 +10 +10 µA

LCN, LCWM, LCV +8 +10

Supply Current Max LJ & LCJ 1.2 3.5 3.5 mA

Drain LCN, LCWM, LCV 1.7 2.0

Electrical Characteristics

REF

10.000 V

unless otherwise noted. Boldface limits apply over temperature, T

MIN

≤T

MAX

. For all other limits

25˚C.

Symbol Parameter Conditions

See

Note

15.75 V

12 V

to 15 V

4.75 V

Limit

Units

Typ

(Note 12)

Tested

Limit

(Note 5)

Design Limit

(Note 6)

Typ

(Note 12)

Tested

Limit

(Note 5)

Design

Limit

(Note 6)

AC CHARACTERISTICS

Current Setting V

0V, V

5V 1.0 1.0 µs

Time

Write and XFER V

0V, V

5V 11 100 250 375 600

Pulse Width Min 9 320 320 900 900

Data Setup Time V

0V, V

5V 9 100 250 375 600

Min 320 320 900 900

Data Hold Time V

0V, V

5V 9 30 50 ns

Min 30 50

Control Setup Time V

0V, V

5V 9 110 250 600 900

Min 320 320 1100 1100

Control Hold Time V

0V, V

5V 9 0 0 10 00

Min 00

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating

the device beyond its specified operating conditions.

Note 2: All voltages are measured with respect to GND, unless otherwise specified.

www.national.com 4

Electrical Characteristics (Continued)

Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by T

JMAX

, θ

, and the ambient temperature, T

. The maximum

allowable power dissipation at any temperature is P

JMAX

−T

)/θ

or the number given in the Absolute Maximum Ratings, whichever is lower. For this device,

JMAX

125˚C (plastic) or 150˚C (ceramic), and the typical junction-to-ambient thermal resistance of the J package when board mounted is 80˚C/W. For the N pack-

age, this number increases to 100˚C/W and for the V package this number is 120˚C/W.

Note 4: For current switching applications, both I

OUT1

and I

OUT2

must go to ground or the “Virtual Ground” of an operational amplifier. The linearity error is degraded

by approximately V

REF

. For example, if V

REF

10Vthena1mVoffset, V

,onI

OUT1

or I

OUT2

will introduce an additional 0.01

linearity error.

Note 5: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 6: Guaranteed, but not 100

production tested. These limits are not used to calculate outgoing quality levels.

Note 7: Guaranteed at V

REF

10 V

and V

REF

Note 8: The unit “FSR” stands for “Full Scale Range.” “Linearity Error” and “Power Supply Rejection” specs are based on this unit to eliminate dependence on a par-

ticular V

REF