Altera Complete Design Suite Release 9.0 README.TXT
=================================================================
This readme.txt file accompanies the Quartus II software version 9.0.
Although we have made every effort to ensure that this version
of the Altera(R) software functions correctly, there may be
problems that we haven't encountered. If you have a question or
problem that is not answered by the information provided in
this readme.txt file, please contact Altera support at
1-800-800-EPLD or submit a Service Request at mysupport.altera.com.
This readme.txt file contains the following information:
* Location of Additional Information -- tells you where to find
additional information about the Altera Complete Design Suite
* Package Contents -- describes the contents of the Altera Complete
Design Suite
* System Requirements -- describes the system requirements for the
components of the Altera Complete Design Suite
Location of Additional Information
==================================
You can find additional information about the Altera Complete
Design Suite at the following locations:
Release Notes -- for information about new features, known issues
and workarounds, timing model status, device support status,
revision history, and supported versions of other EDA tools, please
refer to the Quartus II Software Release Notes, the Nios II EDS
Release Notes, and the MegaCore IP Release Notes, available from the
Literature page of the Altera website.
Errata sheets that describe known issues with Altera MegaCore
functions and Nios II EDS are available from the Literature page
of the Altera website.
Installation & Licensing -- for information about installing and
licensing your Altera design software, please refer to the
Quartus II Installation & Licensing for Windows and Linux Workstations
manual, available from the Literature page of the Altera website.
Package contents
================
The Altera Complete Design Suite contains the following tools:
* Quartus II Design Software including SOPC Builder and MegaCore IP Library
* ModelSim-Altera VHDL and Verilog HDL Simulation Tool
* Nios II Embedded Design Suite
* DSP Builder
You can download software tools and documentation
from the Altera Download Center at the following URL:
www.altera.com/download
The Altera Complete Design Suite also contains the following
technical documentation:
Introduction to Quartus II manual
Quartus II Installation & Licensing for Windows and Linux
Workstations manual
Quartus II Handbook
Mentor Graphics ModelSim Support chapter
AN 340: Altera Software Licensing
AN 320: OpenCore Plus Evaluation of Megafunctions
AN 343: OpenCore Evaluation of AMPP Megafunctions
Nios II Processor Reference Handbook
Nios II Software Developer's Handbook
Nios II C2H Compiler User Guide
You can download the most current versions of these
documents from the Literature pages of the Altera website
at www.altera.com.
System Requirements
===================
Software requirements
---------------------
The Quartus II Design Software is supported on the
following operating systems and versions:
Windows XP SP2 32-bit
Windows XP SP2 64-bit
Windows XP Pro X64 Edition
Windows Vista 64-bit
Windows Vista 32-bit
Red Hat Enterprise Linux 4.0 for 32-bit and for AMD64
or Intel EMT64 64-bit CPUs
Red Hat Enterprise Linux 5.0 for 32-bit and for AMD64
or Intel EMT64 64-bit CPUs
SUSE 9 Enterprise Linux
CentOS 4/5 for 32-bit and for AMD64
or Intel EMT64 64-bit CPUs
The ModelSim-Altera VHDL and Verilog HDL Simulation Tool is supported on
the following operating systems and versions:
Windows XP SP2 32-bit
Windows Vista 32-bit
Red Hat Enterprise Linux 4.0 for 32-bit
Red Hat Enterprise Linux 5.0 for 32-bit
SUSE 9 Enterprise Linux 32-bit
The Nios II Embedded Design Suite is supported on the following
operating systems and versions:
Windows XP SP2
Windows XP Pro X64 Edition
Windows Vista 32-bit
Windows Vista 64-bit
Red Hat Linux Enterprise 4.0 for 32-bit and for AMD64
or Intel EMT64 64-bit CPUs
Red Hat Enterprise Linux 5.0 for 32-bit and for AMD64
or Intel EMT64 64-bit CPUs
SUSE 9 Enterprise Linux
The Altera MegaCore IP Library is supported on the following
operating systems and versions:
Windows XP SP2 32-bit
Windows XP SP2 64-bit
Windows XP Pro X64 Edition
Windows Vista 64-bit
Windows Vista 32-bit
Red Hat Linux 4.0 for 32-bit and for AMD64
or Intel EMT64 64-bit CPUs
Red Hat Linux 5.0 for 32-bit and for AMD64
or Intel EMT64 64-bit CPUs
SUSE 9 Enterprise Linux
CentOS 4/5 for 32-bit and for AMD64
or Intel EMT64 64-bit CPUs
Some MegaCore functions do not support all the listed operating
systems. Refer to the user guide for the individual MegaCore
function. Additional software, such as MATLAB, is required for
some MegaCore functions. Refer to the User Guide for the
individual MegaCore function.
DSP Builder is supported on the following operating systems and
versions:
All operating systems supported by the Quartus II software version 9.0.
The following additional software is required to run DSP Builder:
The MathWorks releases R2007b, R2008a, R2008b, or R2009a
(only the 32-bit versions are supported)
The DSP Builder Advanced blockset uses Simulink fixed-point
types for all operations and requires licensed versions of the
Simulink Fixed-Point Blockset and Fixed-Point Toolbox.
The Signal Processing Blockset is also recommended and is used
in many of the demonstration designs.
Quartus II software version 9.0
Browser
The Quartus II software uses a web browser to display the
interactive tutorial and certain other features. If your
operating system does not provide a default browser, you must
configure a web browser in the Internet Connectivity page of
the Options dialog box.
FLEXlm
The Altera Complete Design Suite uses the FLEXlm license server
software to support network (multiuser) licensing.
If it is not installed, the Quartus II installation process
installs it automatically. However, if you already have FLEXlm
license server software installed for an application other than
the Quartus II or MAX+PLUS(R) II software, you should verify
that the version is Flexlm 9.5 or later.
Display Manager
Linux
KDE version included in Red Hat distribution
Gnome version included in Red Hat distribution
Hardware requirements/recommendations
-------------------------------------
Pentium III or later for Windows or Linux
Color display capable of 1024 X 768 pixel resolution
DVD-ROM drive
One or more of the following I/O ports:
- USB port (if using Windows XP or Windows 2000) for
USB-Blaster(TM) or MasterBlaster(TM)
communications cables, or APU programming unit
- Parallel port for ByteBlasterMV(TM) or
ByteBlaster(TM) II download cables
- Serial port for MasterBlaster communications cable
Memory requirements/recommendations
-----------------------------------
Please see the Quartus II Device Support Release Notes for
information on memory requirements and recommendations.
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西电EDA作业电子琴文件.zip
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西安电子科技大学EDA实验课程大作业,电子琴代码 本课程设计主要是基于VHDL文本输入法设计乐曲演奏电路,该系统基于计算机中时钟分频器的原理,采用自顶向下的设计方法来实现,通过按键输入来控制音响或者自动演奏已存入的歌曲。系统由乐曲自动演奏模块、音调发生模块和数控分频模块三个部分组成。系统实现是用硬件描述语言VHDL按模块化方式进行设计,然后进行编程、时序仿真、电路功能验证,奏出美妙的乐曲(当然由于条件限制,暂不进行功能验证,只进行编程和时序仿真)。该设计最重要的一点就是通过按键控制不同的音调发生,每一个音调对应不同的频率,从而输出对应频率的声音。
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西电EDA作业电子琴文件.zip (174个子文件)
UP3_Board.ptf.4.01 52KB
dianzi_global_asgn_op.abo 94KB
dianzi.root_partition.cmp.atm 15KB
dianzi.root_partition.map.atm 11KB
UP3_Board.ptf.bak 52KB
pin_assign.tcl.bak 3KB
m_freq.vhd.bak 2KB
keyboard.vhd.bak 2KB
reg16.bdf 54KB
crc_mux.bdf 30KB
crc.bdf 28KB
xor_shift_crc16_ccitt.bdf 20KB
endian_convert.bdf 18KB
nios2_in_up3.bdf 13KB
UP3_Board_top.bdf 12KB
NiosII_lab.bdf 12KB
Block2.bdf 5KB
dianzi.bdf 4KB
for_UP3.bsf 4KB
SystemTop.bsf 2KB
UP3_Board.bsf 2KB
crc.c 6KB
crcdma.c 3KB
crcci.c 3KB
simple.c 1KB
pwm.c 1KB
Block2.eco.cdb 161B
NiosII_lab.eco.cdb 160B
jtag_uart_0_input_stream.dat 10B
jtag_uart_0_input_mutex.dat 3B
jtag_uart_0_output_stream.dat 0B
dianziqin.db_info 137B
Block2.db_info 137B
dianzi.db_info 137B
NiosII_lab.db_info 136B
Block2.tis_db_list.ddb 174B
dianzi.root_partition.cmp.dfp 33B
Designing with Quartus Labs2.doc 8.35MB
EDA_电子琴课程设计.doc 218KB
八音符电子琴.doc 133KB
EDA_UP3扩展板信号对应关系表.doc 51KB
5P4.doc 421KB
VHDL.doc 207KB
音乐发生器及简单电子琴的eda设计.doc 147KB
NiosII_lab.done 26B
UP3_Board.done 26B
dianzi.done 26B
dianzi.dpf 239B
Block2.dpf 239B
dianzi.root_partition.map.dpi 911B
UP3_Board.fit.eqn 1.11MB
UP3_Board.map.eqn 1013KB
altera_avalon_pwm.h 3KB
Block2.map_bb.hdb 5KB
dianzi.root_partition.cmp.hdbx 3KB
dianzi.root_partition.map.hdbx 3KB
firmware_ROM.hex 8KB
data_RAM.hex 34B
payload_buffer.hex 30B
Block2.hif 248B
cmp_state.ini 2B
cmp_state.ini 2B
dianzi.root_partition.map.kpt 8KB
dianzi.root_partition.cmp.kpt 341B
dianzi.root_partition.cmp.logdb 4B
rf_ram.mif 600B
cpu_0.ocp 808B
UP3 Manual.pdf 1.27MB
FlipFlop Tutorial.pdf 1.13MB
UP3 Reference Manual.pdf 1.07MB
Designing_NiosII_Sys_For_UP3.pdf 678KB
Designing_NiosII_Sys_For_UP3.pdf 678KB
Designing_NiosII_Sys_For_UP3.pdf 678KB
USB_2.0_IP_UserGuide.pdf 424KB
UP3_1C6_REV2_Schematic.pdf 369KB
dianzi.pin 30KB
UP3_Board.pin 30KB
mk_sram.pl 4KB
mk_sram.pl 4KB
dianzi.pof 512KB
nios2_in_up3.pof 512KB
UP3_Board.pof 512KB
EDA实验--集成开发平台Quartus_II操作基础.ppt 1.97MB
UP3_Board.ptf 52KB
SystemTop.ptf 42KB
class.ptf 11KB
class.ptf 8KB
class.ptf 810B
dianziqin_assignment_defaults.qdf 46KB
dianzi_assignment_defaults.qdf 46KB
UP3_Board_assignment_defaults.qdf 29KB
NiosII_lab_assignment_defaults.qdf 29KB
prev_cmp_dianzi.qmsg 94KB
prev_cmp_dianzi.tan.qmsg 44KB
prev_cmp_dianzi.fit.qmsg 37KB
prev_cmp_dianzi.map.qmsg 5KB
Block2.map.qmsg 5KB
prev_cmp_dianzi.asm.qmsg 2KB
nios2_in_up3.qpf 2KB
NiosII_lab.qpf 2KB
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