BL24C256超高性价比EEPOM,SOIC8,TSSOP8两种封装都有。-BL24C256A.PDF

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BL24C256A 256Kbits (32768×8)

BL24C256A 256Kbits (32768×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited

1-18

Features

 Compatible with all I

C bidirectional data

transfer protocol

 Memory array:

– 256 Kbits (32 Kbytes) of EEPROM

– Page size: 64 bytes

– Additional Write lockable page

 Single supply voltage and high speed:

– 1 MHz （2.5V）

– 400 KHz（1.7V）

– 100 KHz（1.7V）

Random and sequential Read modes

 Write:

– Byte Write within 3 ms

– Page Write within 3 ms

– Partial Page Writes Allowed

 Write Protect Pin for Hardware Data Protection

 Schmitt Trigger, Filtered Inputs for Noise

Suppression

 High-reliability

– Endurance: 1 Million Write Cycles

– Data Retention: 100 Years

 Enhanced ESD/Latch-up protection

– HBM 8000V

 8-lead PDIP/SOP/TSSOP/UDFN and WLCSP4

packages

Description

 The BL24C256A provides 262144 bits of serial

electrically erasable and programmable read-

only memory (EEPROM), organized as 32768

words of 8 bits each.

 The device is optimized for use in many

industrial and commercial applications where

low-power and low-voltage operation are

essential.

 The BL24C256A offers an additional page,

named the Identification Page (64 bytes). The

Identification Page can be used to store

sensitive application parameters which can be

(later) permanently locked in Read-only mode.

Pin Configuration

GND

VCC

GND

VCC

１

２

３

４

５

６

７

８

１

２

３

４

１

２

３

４

５

６

７

８

５

６

７

８

５

６

７

８

１

２

３

４

８-lead PDIP ８-lead SOP ８-lead TSSOP ８-pad DFN

1 2

Vcc

Vss

SCL

SDA

WLCSP4

Bottem view

Marking side

(top view)

SCL

SDA

SCL

SDA

SCL

SDA

SCL

SDA

BL24C256A 256Kbits (32768×8)

BL24C256A 256Kbits (32768×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited

3-18

WRITE PROTECT (WP): The BL24C256A has a Write Protect pin that provides hardware data protection.

The Write Protect pin allows normal read/write operations when connected to ground (GND). When

the Write Protection pin is connected to Vcc, the write protection feature is enabled and operates as

shown in the following Table 2.

WP Pin Status BL24C256A

At VCC Full(256K)Array

At GND Normal Read/Write Operations

Functional Description

1. Memory Organization

BL24C256A, 256K SERIAL EEPROM: Internally organized with 256 pages of 64 bytes each, the 256K

requires a 15-bit data word address for random word addressing.

2. Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the

SDA pin may change only during SCL low time periods (see Figure 2). Data changes during SCL high

periods will indicate a start or stop condition as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must

precede any other command (see Figure 3).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read

sequence, the stop command will place the EEPROM in a standby power mode (see Figure 3).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit

words. The EEPROM sends a "0" to acknowledge that it has received each word. This happens during

the ninth clock cycle.

STANDBY MODE: The BL24C256A features a low-power standby mode which is enabled: (a) upon power-

up and (b) after the receipt of the STOP bit and the completion of any internal operations.

MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be

reset by following these steps:

1. Clock up to 9 cycles.

2. Look for SDA high in each cycle while SCL is high.

3. Create a start condition.

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