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SERCON816 Specification.pdf
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SERCON816 Specificationpdf,SERCON816 Specification
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1 © 1999 SICAN Braunschweig GmbH SERCON816
Company Confidential Version 1.3 from 30/07/1999
SERCON816
Specification
Project: sertrans
Version 1.3
Document: /proj/sertrans/doc/spec/sp81613doc
Contents
2 © 1999 SERCOS interface e. V. SERCON816
Version 1.3 from 30/07/1999
Author(s): Rolf Kassa / R. Marzak – STMicroelectronics (Translation)
Rigobert Kynast (TWG-IGS)
Responsible:
Department: DIC
Revision History:
Version
Date
Remarks
1.0 4/12/1998 Proposal
1.1 17/12/1998 1. Revision
1.2 15/03/1999 2. Revision / Update of implemented changes
1.3 11/5/1999 Document of Work, Bitrate
Contents
SERCON816 © 1999 SERCOS interface e. V. 3
Version 1.3 from 30/07/1999
INDEX
1 Overview........................................................................................... 4
1.1 Introduction................................................................................................................. 4
1.2 Cross Reference........................................................................................................ 4
2 Specification SERCON816 ............................................................ 5
2.1 Technology................................................................................................................. 5
2.2 Pinning........................................................................................................................ 5
2.3 Seriell Interface........................................................................................................... 5
2.3.1 Seriell Clock (SCLK)............................................................................................ 5
2.3.2 SERCON410B Compatible Mode ....................................................................... 6
2.3.3 Repeater.............................................................................................................. 7
2.4 Telegram Processing................................................................................................. 7
2.4.1 Clock for Telegram Processing (MCLK)............................................................. 7
2.5 Dual Port RAM............................................................................................................ 7
2.6 Watchdog................................................................................................................... 8
2.6.1 Watchdog Output WDOGN................................................................................. 9
2.6.2 Watchdog Influence to Telegram Processing..................................................... 9
2.6.3 Trigger Intervall .................................................................................................. 10
2.6.4 Trigger by Software ........................................................................................... 10
2.6.5 Trigger by CYC_CLK......................................................................................... 10
2.7 Output DIV_CLK....................................................................................................... 11
2.8 Bug fix „Specification BUSY-Signal“ ........................................................................ 12
2.9 Bug fix „Phase 1,2 Error“ ......................................................................................... 12
2.9.1 Error Description ............................................................................................... 12
2.9.2 Reason and Fix of Error .................................................................................... 13
2.10 Bugfix „Asynchronous Access to Dual-Port-RAM“ ............................................... 13
2.10.1 Controlling the Double Buffer (VAL-Bit) ......................................................... 14
2.10.2 Control Word for Service-Container.............................................................. 15
2.11 Control Register.................................................................................................... 16
2.11.1 Changed Control Register............................................................................. 16
2.11.2 SERCON816 NEW Control Registers.......................................................... 18
FIGURES
Figure 1: Watchdog Interrupt................................................................................................. 8
Figure 2: Reset Processor via Output WDOGN................................................................... 9
Figure 3: Watchdog Trigger by MST.................................................................................... 10
Figure 4: New Mode DIV_CLK............................................................................................. 12
Figure 5: FLMDTADR .......................................................................................................... 13
Figure 6: Read/Write of VAL-Bit when Sending Telegrams............................................... 14
Figure 7: Interrupt RSCEND ................................................................................................ 16
Contents
4 © 1999 SERCOS interface e. V. SERCON816
Version 1.3 from 30/07/1999
1 Overview
1.1 Introduction
The new SERCON816 ASIC is the next generation of SERCON interface controller
following the SERON410B. The goal was to develop an ASIC to be down compatible
with the existing SERCON410B but to offer essentially enhanced features. The
SERCON410B ASIC is manufactured in the 0.7µm HCMOS technology, where as
the new SERCON816 ASIC is manufactured in the 0.5µm/5V HCMOS technology of
STMicroelectronics.
Aside of transferring the technology, following enhancements of features and
functions are implemented as well:
• Increase of serial transmission rate from 2 and 4 MBit/s to 2, 4, 8 and 16 MBit/s.
External clock generation is not necessary anymore. Speed of parallel data
processing (telegram processing) is increased accordingly.
• Double internal Dual Port RAM (DPRAM) from 1K words to 2K words
• Introduction of Watchdog to monitor software and external synchronization
signals.
• Reset value for Repeater Mode of the serial interface is configurable through input
pins.
• New Mode of output DIV_CLK
Using the SERCON410B, some irregular behavior can be observed in some
operating modes, which limits the usage ability. Following errors will be corrected in
the new SERCON816.
• Specification of BUSY signal
The timing of this signal is described in a wrong way in the actual specification.
The new data sheet for the SERCON816 will be modified accordingly.
• Constantly sending of drive data telegrams (AT) during phase 1 and 2:
if a drive is requested to send AT’s, this will not be done once, but repeated
constantly.
• Asynchronous Access to DPR:
if data are written at any time during the transmission cycle into the Dual Port
RAM via the bus interface, it can happen, that these data are been over written by
the internal telegram processing. This issue will not be solved generally. Instead
of this a work around will be implemented for two types of data that turned out to
be the most critical is real applications.
1.2 Cross Reference
This delta specification is based on following documents:
• SERCON410B Reference Manual (08/93)
• Protocol of Meeting at ST on 17.11.98
• Extended offer by 5.3.99
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