基于RTL的VHDL模拟器的验证与实现研究
62 浏览量
2021-02-24
10:23:38
上传
评论
收藏 324KB PDF 举报
Energy Procedia 16 (2012) 522 – 527
1876-6102 © 2011 Published by Elsevier B.V. Selection and/or peer-review under responsibility of International Materials Science Society .
doi:10.1016/j.egypro.2012.01.084
A
vailable online at www.sciencedirect.com
Energy
Procedia
Energy Procedia 00 (2011) 000–000
www.elsevier.com/locate/procedia
Research on Verification and Implementation of RTL-based
VHDL Simulator
Leng Ming*, Sun Ling-yu
Department of Computer Science, Jinggangshan University, Ji’an 343009, China
Abstract
VHDL simulator based on Register Transfer Level (RTL) is implemented and verified, named RVS. Firstly, we give
the implementation of RVS. Secondly, we design the micro program SAP-CPU and logic SAP-CPU based on VHDL
language, which includes the format of control instruction, instruction set, addressing method, test program and the
architecture of logic SAP-CPU and micro program SAP-CPU. Finally, the experiment and analysis show that the
simulator of RVS perform well and produce encouraging solutions correctly on two SAP-CPU designs controlled by
combinational logic and micro-program.
© 2011 Published by Elsevier Ltd. Selection and/or peer-review under responsibility of [name organizer]
Register Transfer Level; VHDL Language; Simulation; Verification; Implementation.
1. Introduction
The technology of Microelectronic has accelerated the development of modern society. As the core of
computer, microprocessor has been applied in various areas. With the development of microprocessor
technology, traditional methods of logic design couldn’t meet the needs of design and have been replaced
by EDA method step by step. But EDA method is also faced with challenge of high complexity of design.
VHDL and Verilog, as the most representative HDL, which is a formalization language used to describe
the function of hardware circuit, is a powerful and standardized HDL. In the context of increasing need
for LSL design, more and more attention and popularization from the industry make HDL, an
international standard language, the primary HDL in hardware design
[1]
. Essential to HDL design is the
ability to simulate HDL programs. Simulation allows an HDL description of a design to pass design
verification, an important milestone that validates the design's intended function against the code
implementation in the HDL description
[2]
.
In [3], we design a VHDL simulator based on RTL, which inputs the VLSI design described by VHDL
language of RTL, generates intermediate code by the corresponding compiler, reads the external
excitation signal from the waveform file and applies it on the behavior model. We can decide whether a
Available online at www.sciencedirect.com
© 2011 Published by Elsevier B.V. Selection and/or peer-review under responsibility of International Materials Science Society.
评论0
最新资源