Contents lists available at ScienceDirect
Materials Science in Semiconductor Processing
journal homepage: www.elsevier.com/locate/mssp
Trapping analysis and countermeasure for arsenic auto-doping in 40-nm
epitaxial diode arrays and CMOS integration
Yan Liu
a,
⁎
, Heng Wang
a,b
, Bo Liu
a,c
, Yan Cheng
a
, Sannian Song
a
, Liangcai Wu
a
, Dong Zhou
d
,
Zhitang Song
a
a
State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences, Shanghai
200050, China
b
University of Chinese Academy of Sciences, Beijing 100049, China
c
Suzhou University of Science and Technology, School of Chemical Biology and Materials Engineering, Suzhou 215009, Jiangsu Province, China
d
Key Laboratory of Functional Materials and Devices for Special Environments, Xinjiang Technical Institute of Physics and Chemistry, Chinese Academy of Sciences,
Urumqi 830011, China
ARTICLE INFO
Keywords:
As Auto-doping mechanism
Epitaxial growth
Diode array drivability
Process compatibility
ABSTRACT
In this work, a methodology to analyze trapping mechanism of As auto-doping has been presented in the epi-
taxial diode array and CMOS integration. With a temperature-pressure optimization in three-step silicon epi-
taxial growth being proposed, As trapping mechanism has been revealed and auto-doping effect has been sup-
pressed efficiently. Most importantly, the shifting CMOS devices are adjusted to meet the 40-nm Wafer
Acceptance Test (WAT) target value according to technology computer aided design (TCAD) simulation results.
High-resolution transmission electron microscopy (HRTEM) image reveals that the periodical lattice structure of
silicon epitaxy has been formed in this three-step epitaxial growth. As surface and bulk auto doping profiles of in
diode array and CMOS regions have been investigated by secondary ion mass spectroscopy (SIMS). It demon-
strated that As auto-doping effect can be suppressed by higher temperature of 1100 ℃ and lower background
partial pressure of 10 Torr in the capping and main epitaxy deposition respectively, without compromising
epitaxial film quality. According to the optimal diode array process, normalized buried N+ layer (BNL) doping
level of 4.5 has been employed to achieve lower word-line (WL) series resistance of
6
0Ω/sq
, and higher on-
current density of
× Acm
1
.47 10 /
72
in
×
1
61
6
bits 4F
2
diode array.
1. Introduction
Today, non-volatile memories are getting an exponential demand
when our life is moving in a new digital era, and are fundamental in the
definition of all the electronic portable devices and systems in our daily
life. A huge number of semiconductor manufacturers, including IBM,
Micron, and Samsung, are tending to put their mainstream technology
platforms on embedded memory solutions. Phase-change random ac-
cess memory (PCRAM) is no exception, and scientists spare no efforts to
develop embedded PCRAM to satisfy the high reliability applications
such as Internet of Things (IoT), wearables, smart devices and sensor
hubs in 40-nm standard CMOS technology and beyond. Hitachi and
Renesas Technology [1] co-developed 512 KB embedded phase-change
memory in 2007, which is switched by MOSFET. And likewise, in 2012,
STMicroelectronics collaborated with Numonyx [2] developed 4MB
embedded phase-change memory chip accessed by MOSFET. In IEDM
2016, IBM/Macronix Phase Change Memory Joint project [3] has
announced their 128MB embedded PCM chip design. It is very di fferent
that, in our embedded diode-switched PCRAM process scheme, diode
array would be fabricated with periphery CMOS circuit synchronously
on the silicon epitaxial layer. The vertical diode-switched PCRAM
(1D1R) using dual trench epitaxial technology [4] has achieved
minimum cell size (5F
2
) and cross-talk immunity in memory array.
Therefore, the compatibility of diode array and CMOS periphery circuit
integration is essential of embedded PCRAM chip design.
Other than selective epitaxial growth polysilicon diode-switched
scheme from Samsung [5], we have adopted a cost-effective approach
that the diode array and CMOS devices are fabricated on silicon epi-
taxial layer simultaneously. Hence, it is noteworthy that the electrical
characteristics of diode array and MOSFET are determined by this high
quality silicon epitaxial layer. As reported in our previous work [6], the
buried N
+
layer (BNL) as low-resistance word-line (WL) defines diode
array region, while the CMOS region locates in the outside of BNL re-
gion (diode region). Then an approximately intrinsic silicon epitaxial
http://dx.doi.org/10.1016/j.mssp.2017.08.021
Received 28 April 2017; Received in revised form 10 August 2017; Accepted 15 August 2017
⁎
Corresponding author.
E-mail addresses: yanliu@mail.sim.ac.cn (Y. Liu), liubo@mail.sim.ac.cn (B. Liu).
Materials Science in Semiconductor Processing 71 (2017) 326–331
1369-8001/ © 2017 Elsevier Ltd. All rights reserved.
MARK
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