Abstract
This thesis addresses performance problems in hardware lock elision (HLE), which is being
introduced into commercial processors. Using Intel’s Haswell HLE as a study vehicle, we show that
even a few transactional aborts can severely limit the amount of concurrency and speedup obtained
using HLE. We then provide a software-based technique to solve this problem and restore the lost
potential concurrency in lock elision executions.
We present a lock elision approach based on Haswell’s transactional memory support that
serializes only conflicting threads, allowing non-conflicting threads to continue their speculative run.
To do this we add a serializing path to the lock implementation, in which a thread experiencing a
conflict acquires a distinct auxiliary lock (without using lock elision) and then rejoins the speculative
execution.
We evaluate our methods on a Haswell processor, using a set of data structure benchmarks
and applications from the STAMP suite. Our methods lead to performance improvement of up to
3.5× on STAMP and up to 10× on the data structure benchmarks, compared to using Haswell’s
hardware lock elision as is.
We also describe how to extend Haswell’s HLE mechanism to achieve a similar effect to our
software-assisted scheme entirely in hardware, by distinguishing between conflicts on the lock and
on the data cache lines. Our proposal requires no cache-coherence protocol changes.
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