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TEL-AVIV UNIVERSITYRAYMOND AND BEVERLY SACKLERFACULTY OF EXACT SCIENCESSCHOOL OF COMPUTER SCIENCEProgramming with Hardware Lock ElisionDissertation submitted in partial fulfillment of the requirements for the M.Sc.degree in the School of Computer Science, Tel-Aviv UniversitybyAmir LevyThe research work for this thesis has been carried out at Tel-Aviv Universityunder the supervision of Prof. Yehuda Afekand the consultation of Mr. Adam MorrisonSeptember 2013AbstractThis thesis addresses performanc
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TEL-AVIV UNIVERSITY
RAYMOND AND BEVERLY SACKLER
FACULTY OF EXACT SCIENCES
SCHOOL OF COMPUTER SCIENCE
Programming with
Hardware Lock Elision
Dissertation submitted in partial fulfillment of the requirements for the M.Sc.
degree in the School of Computer Science, Tel-Aviv University
by
Amir Levy
The research work for this thesis has been carried out at Tel-Aviv University
under the supervision of Prof. Yehuda Afek
and the consultation of Mr. Adam Morrison
September 2013
Abstract
This thesis addresses performance problems in hardware lock elision (HLE), which is being
introduced into commercial processors. Using Intel’s Haswell HLE as a study vehicle, we show that
even a few transactional aborts can severely limit the amount of concurrency and speedup obtained
using HLE. We then provide a software-based technique to solve this problem and restore the lost
potential concurrency in lock elision executions.
We present a lock elision approach based on Haswell’s transactional memory support that
serializes only conflicting threads, allowing non-conflicting threads to continue their speculative run.
To do this we add a serializing path to the lock implementation, in which a thread experiencing a
conflict acquires a distinct auxiliary lock (without using lock elision) and then rejoins the speculative
execution.
We evaluate our methods on a Haswell processor, using a set of data structure benchmarks
and applications from the STAMP suite. Our methods lead to performance improvement of up to
3.5× on STAMP and up to 10× on the data structure benchmarks, compared to using Haswell’s
hardware lock elision as is.
We also describe how to extend Haswell’s HLE mechanism to achieve a similar effect to our
software-assisted scheme entirely in hardware, by distinguishing between conflicts on the lock and
on the data cache lines. Our proposal requires no cache-coherence protocol changes.
iii
Acknowledgements
I am deeply grateful to my advisor, Prof. Yehuda Afek for his insightful comments, suggestions
and warm encouragement. I would particularly like to thank Mr. Adam Morrison, I have greatly
benefited from our joint work.
Finally, I would like to thank my wife Noga for her constant and consistent support, encour-
agement and good advice during the accomplishment of this work and in general.
iv
Contents
1 Introduction 1
2 Transactional Synchronization Extensions 5
2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Haswell’s TSX Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 HLE Avalanche Effect 9
4 Software-Assisted Conflict Management 16
5 Evaluation 22
5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2 Red-black Tree Data Structure Benchmark . . . . . . . . . . . . . . . . . . . . . . . 23
5.3 STAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6 Adjusting Fair Locks to Work with HLE 29
6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2 Ticket Lock Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3 CLH Lock Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.4 Lock Adjustments Correctness Proofs . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7 Extending Haswell’s HLE Implementation 35
8 Related work 39
v
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