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Al2O3 / SiO2叠层电介质的4H SiC金属绝缘半导体结构的研究
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原子层沉积(ALD)Al2O3 /干氧化超薄SiO2膜作为高k栅极电介质生长在硅上本文研究了8°离轴4H-SiC(0001)外延晶片。 金属-绝缘-半导体(MIS) 分别制造并比较了具有不同栅极介电叠层(Al2O3 / SiO2,Al2O3和SiO2)的电容器彼此。 I–V测量表明,Al2O3 / SiO2堆具有较高的击穿场(12 MV / cm) 与SiO2相当,并且在4 MV / cm的电场下具有110-7 A / cm2的相对较低的栅极泄漏电流到Al2O3。 1 MHz的高频C–V测量表明,Al2O3 / SiO2叠层具有较小的正值平带电压漂移和磁滞电压,表明界面附近的有效电荷和慢阱密度较低。
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Chin. Phys. B Vol. 21, No. 8 (2012) 087701
Investigation of 4H SiC metal insulation semiconductor
structure with Al
2
O
3
/SiO
2
stacked dielectric
∗
Tang Xiao-Yan(汤晓燕)
†
, Song Qing-Wen(宋庆文), Zhang Yu-Ming(张玉明),
Zhang Yi-Men(张义门), Jia Ren-Xu(贾仁需), L¨u Hong-Liang(吕红亮), and Wang Yue-Hu(王悦湖)
School Microelectronics, Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices,
School of Microelectronics, Xidian University, Xi’an 710071, China
(Received 10 February 2012; revised manuscript received 22 February 2012)
Atomic layer deposited (ALD) Al
2
O
3
/dry-oxidized ultrathin SiO
2
films as high-k gate dielectric grown on the
8
◦
off-axis 4H–SiC (0001) epitaxial wafers are investigated in this paper. The metal–insulation–semiconductor (MIS)
capacitors, respectively with different gate dielectric stacks (Al
2
O
3
/SiO
2
, Al
2
O
3
, and SiO
2
) are fabricated and compared
with each other. The I–V measurements show that the Al
2
O
3
/SiO
2
stack has a high breakdown field (≥12 MV/cm)
comparable to SiO
2
, and a relatively low gate leakage current of 1×10
−7
A/cm
2
at electric field of 4 MV/cm comparable
to Al
2
O
3
. The 1-MHz high frequency C–V measurements exhibit that the Al
2
O
3
/SiO
2
stack has a smaller positive
flat-band voltage shift and hysteresis voltage, indicating less effective charge and slow-trap density near the interface.
Keywords: 4H–SiC, Al
2
O
3
, high-k dielectric
PACS: 77.22.Jp, 73.20.–r, 77.84.Lf DOI: 10.1088/1674-1056/21/8/087701
1. Introduction
Metal–oxide–semiconductor field-effect transis-
tors (MOSFETs) based on 4H–SiC have been inten-
sively investigated for high power device applications
because of the excellent physical and electronic prop-
erties of 4H–SiC.
[1−3]
However, the relatively low di-
electric constant of the native oxide SiO
2
(3.9) com-
pared with that of SiC(9.8) can contribute to severe
oxide breakdown and reliability issues,
[4]
because an
electric field as high as approximately 2.5 times is im-
posed on the oxide rather than on the SiC. Recently,
extensive investigations have focused on searching for
a suitable alternative high-k dielectric
[5−8]
to reduce
the electric field in the gate dielectric layer. However,
one challenge exists in applying high-k gate dielec-
tric materials, in which the low band offset between
high-k and SiC material results in high leakage cur-
rent. To solve this problem, an ultrathin SiO
2
interfa-
cial layer is usually introduced between high-k dielec-
tric and SiC.
[9]
Aluminium oxide (Al
2
O
3
) is attractive
as an alternative gate dielectric because it simultane-
ously presents a dielectric constant of 9 and a large
band offset to 4H–SiC in comparison with other high-
k materials.
[9]
In the present paper, atomic layer deposition
(ALD) high-k gate dielectric Al
2
O
3
and SiO
2
stacked
films on the 8
◦
off-axis 4H–SiC (0001) epitaxial wafers
are studied. The ultrathin SiO
2
interfacial layer is
formed by dry-oxygen oxidation. The electrical char-
acteristics are investigated by current voltage (I–V ),
and high frequency (HF) capacitance voltage (C–V )
measurements. Results exhibit that the Al
2
O
3
/SiO
2
stack has attractive characteristics, which are low
leakage current, high breakdown voltage, small pos-
itive flat-band voltage shift, and a very small hystere-
sis voltage, compared with the single Al
2
O
3
or SiO
2
stack on 4H–SiC.
2. Device structure and fabricat-
ing process
Figure 1 shows the schematics of the fabricated
4H–SiC metal–oxide–semiconductor (MOS) capaci-
tors respectively with SiO
2
, Al
2
O
3
, and Al
2
O
3
/SiO
2
stacks. An n-type 10-µm epilayer doped by nitrogen
with a concentration of 3.0 × 10
15
cm
−3
was grown on
each N-type 4H–SiC [0001] 8
◦
off-axis wafer, which is
used to fabricate the MOS capacitor. The wafers were
cleaned with the conventional Radio Corporation of
America (RCA) clean procedure, and then dipped into
∗
Project supported by the National Natural Science Foundation of China (Grant Nos. 61006060 and 61176070).
†
Corresponding author. E-mail: xytang@mail.xidian.edu.cn
c
2012 Chinese Physical Society and IOP Publishing Ltd
http://iopscience.iop.org/cpb
http://cpb.iphy.ac.cn
087701-1
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