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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CDCE62005
SCAS862G –NOVEMBER 2008–REVISED JULY 2016
CDCE62005 3:5 Clock Generator, Jitter Cleaner with Integrated Dual VCOs
1
1 Features
1
• Superior Performance:
– Low Noise Clock Generator: 550 fs rms typical
(10 kHz to 20 MHz Integration Bandwidth),
F
C
= 100 MHz
– Low Noise Jitter Cleaner: 2.6 ps rms typical
(10 kHz to 20 MHz Integration Bandwidth),
F
C
= 100 MHz
• Flexible Frequency Planning:
– 5 Fully Configurable Outputs: LVPECL, LVDS,
LVCMOS and Special High Swing Output
Modes
– Unique Dual-VCO Architecture Supports a
Wide Tuning Range: 1.750 GHz to 2.356 GHz
– Output Frequency Ranges from 4.25 MHz to
1.175 GHz in Synthesizer Mode
– Output Frequency up to 1.5 GHz in Fan-Out
Mode
– Independent Coarse Skew Control on all
Outputs
• High Flexibility:
– Integrated EEPROM Determines Device
Configuration at Power-up
– Smart Input Multiplexer Automatically Switches
Between One of Three Reference Inputs
• 7-mm × 7-mm 48-Pin VQFN Package (RGZ)
• –40°C to +85°C Temperature Range
2 Applications
• Wireless Infrastructure
• Switches and Routers
• Medical Electronics
• Military and Aerospace
• Industrial
3 Description
The CDCE62005 is a high performance clock
generator and distributor featuring low output jitter, a
high degree of configurability via a SPI interface, and
programmable start up modes determined by on-chip
EEPROM. Specifically tailored for clocking data
converters and high-speed digital signals, the
CDCE62005 achieves jitter performance well under 1
ps RMS (10 kHz to 20 MHz integration bandwidth).
The CDCE62005 incorporates a synthesizer block
with partially integrated loop filter, a clock distribution
block including programmable output formats, and an
input block featuring an innovative smart multiplexer.
The clock distribution block includes five individually
programmable outputs that can be configured to
provide different combinations of output formats
(LVPECL, LVDS, LVCMOS). Each output can also be
programmed to a unique output frequency (up to 1.5
GHz) and skew relationship via a programmable
delay block (note that frequency range depends on
operational mode and output format selected). If all
outputs are configured in single-ended mode (for
example, LVCMOS), the CDCE62005 supports up to
ten outputs. Each output can select one of four clock
sources to condition and distribute including any of
the three clock inputs or the output of the frequency
synthesizer. The input block includes two universal
differential inputs which support frequencies in the
range of 40 kHz to 500 MHz and an auxiliary input
that can be configured to connect to an external
crystal via an on chip oscillator block.
The smart input multiplexer has two modes of
operation, manual and automatic. In manual mode,
the user selects the synthesizer reference via the SPI
interface. In automatic mode, the input multiplexer will
automatically select between the highest priority input
clock available.
Device Information
(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
CDCE62005 VQFN (48) 7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Application Example
