# usage_Uart_TX_hw1(數位系統)(use SOL2)
## usage_Uart_TX_hw1
```verilog
`include "Uart_TX.v"
module usage_Uart_TX_hw1(clk_50M, reset_n, write, write_value, uart_txd, finish);
/*--------input/output--------*/
input clk_50M, write, reset_n;
input [7:0]write_value;
output uart_txd, finish;
/*---------variables---------*/
reg [7:0]regdata;
reg [2:0]counter;
reg [12:0]cnt_uart;
reg tick_uart;
wire TX_D, LDEN, SHEN, rstcount, countEN;
/*---------assign wire---------*/
assign uart_txd = (SHEN)?(regdata[0]):(TX_D);
/*---------9600HZ counter---------*/
always@(posedge clk_50M or negedge reset_n)begin
if(!reset_n)cnt_uart <= 13'd0;
else begin
if(cnt_uart<13'd5207)cnt_uart <= cnt_uart + 13'd1;
else cnt_uart <= 13'd0;
end
end
always@(posedge clk_50M or negedge reset_n)begin
if(!reset_n)tick_uart <= 1'b0;
else begin
if(cnt_uart==13'd5206)tick_uart <= 1'b1;
else tick_uart <= 1'b0;
end
end
/*---------Uart_TX instance---------*/
Uart_TX U0(
.clk_50M(clk_50M),
.rst_n(reset_n),
.count(counter),
.rstcount(rstcount),
.countEN(countEN),
.tick_uart(tick_uart),
.TX_D(TX_D),
.LDEN(LDEN),
.SHEN(SHEN),
.en(write),
.finish(finish)
);
/*---------counter---------*/
always@(posedge clk_50M or negedge reset_n)begin
if(!reset_n)counter <= 3'd0;
else begin
if(tick_uart==1'b1)begin
if(rstcount) counter <= 3'd0;
else if(countEN)counter <= counter + 3'd1;
else counter <= counter;
end
else counter <= counter;
end
end
/*---------write_value---------*/
always@(posedge clk_50M or negedge reset_n)begin
if(!reset_n)regdata <= 8'd0;
else begin
if(tick_uart==1'b1)begin
if(LDEN) regdata <= write_value;
el
